Visible to Intel only — GUID: QSF-OPTIMIZE_TIMING
Ixiasoft
Visible to Intel only — GUID: QSF-OPTIMIZE_TIMING
Ixiasoft
OPTIMIZE_TIMING
Controls whether the Fitter optimizes to meet the maximum delay timing requirements (for example, clock cycle time). By default, this option is set to Normal compilation. Turning it off can help fit designs that have extremely high interconnect requirements and can also reduce compilation time, although at the expense of significant timing performance (since the fitter will be ignoring the design's timing requirements). If this option is off, other fitter timing optimization options have no effect (such as Optimize Hold Timing).
Old Name
OPTIMIZE_INTERNAL_TIMING, USE_TIMING_DRIVEN_COMPILATION
Type
Enumeration
Values
- Normal compilation
- Off
Device Support
- Intel Agilex® 5
- Intel Agilex® 7
- Arria® 10
- Cyclone® 10 GX
- Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name OPTIMIZE_TIMING <value>
Default Value
Normal compilation