Visible to Intel only — GUID: mwh1410383720779
Ixiasoft
Visible to Intel only — GUID: mwh1410383720779
Ixiasoft
2.4.1.4. Deriving PLL Clocks
Create Base Clock for PLL input Clock Ports
If your design contains transceivers, LVDS transmitters, or LVDS receivers, use the derive_pll_clocks to constrain this logic in your design and create timing exceptions for those blocks.
create_clock -period 10.0 -name fpga_sys_clk [get_ports fpga_sys_clk] derive_pll_clocks
Include the derive_pll_clocks command in your .sdc file after any create_clock command. Each time the Timing Analyzer reads the .sdc file, the appropriate generated clock is created for each PLL output clock pin. If a clock exists on a PLL output before running derive_pll_clocks, the pre-existing clock has precedence, and an auto-generated clock is not created for that PLL output.
The following shows a simple PLL design with a register-to-register path:
The Timing Analyzer generates messages like the following example when you use the derive_pll_clocks command to constrain the PLL.
derive_pll_clocks Command Messages
Info: Info: Deriving PLL Clocks: Info: create_generated_clock -source pll_inst|altpll_component|pll|inclk[0] -divide_by 2 -name pll_inst|altpll_component|pll|clk[0] pll_inst|altpll_component|pll|clk[0] Info:
The input clock pin of the PLL is the node pll_inst|altpll_component|pll|inclk[0] which is the -source option. The name of the output clock of the PLL is the PLL output clock node, pll_inst|altpll_component|pll|clk[0].
If the PLL is in clock switchover mode, multiple clocks generate for the output clock of the PLL; one for the primary input clock (for example, inclk[0]), and one for the secondary input clock (for example, inclk[1]). Create exclusive clock groups for the primary and secondary output clocks since they are not active simultaneously.
You can verify correct implementation of clock constraints by using Report Clocks (report_clocks) to generate clock timing reports. You can use Check Timing (check_timing) to report problems with a variety of timing constraints, such as the number of instances where clocks that are assigned to a PLL do not correspond properly with the PLL settings you define in design files.