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1.2.1. Timing Path and Clock Analysis
1.2.2. Clock Setup Analysis
1.2.3. Clock Hold Analysis
1.2.4. Recovery and Removal Analysis
1.2.5. Multicycle Path Analysis
1.2.6. Metastability Analysis
1.2.7. Timing Pessimism
1.2.8. Clock-As-Data Analysis
1.2.9. Multicorner Timing Analysis
1.2.10. Time Borrowing
2.1. Using Timing Constraints throughout the Design Flow
2.2. Timing Analysis Flow
2.3. Applying Timing Constraints
2.4. Timing Constraint Descriptions
2.5. Timing Report Descriptions
2.6. Scripting Timing Analysis
2.7. Using the Quartus® Prime Timing Analyzer Document Revision History
2.8. Quartus® Prime Pro Edition User Guide: Timing Analyzer Archive
2.4.4.5.1. Default Multicycle Analysis
2.4.4.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0
2.4.4.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1
2.4.4.5.4. Same Frequency Clocks with Destination Clock Offset
2.4.4.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency
2.4.4.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
2.4.4.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency
2.4.4.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
2.5.1. Report Fmax Summary
2.5.2. Report Timing
2.5.3. Report Timing By Source Files
2.5.4. Report Data Delay
2.5.5. Report Net Delay
2.5.6. Report Clocks and Clock Network
2.5.7. Report Clock Transfers
2.5.8. Report Metastability
2.5.9. Report CDC Viewer
2.5.10. Report Asynchronous CDC
2.5.11. Report Logic Depth
2.5.12. Report Neighbor Paths
2.5.13. Report Register Spread
2.5.14. Report Route Net of Interest
2.5.15. Report Retiming Restrictions
2.5.16. Report Register Statistics
2.5.17. Report Pipelining Information
2.5.18. Report Time Borrowing Data
2.5.19. Report Exceptions and Exceptions Reachability
2.5.20. Report Bottlenecks
2.5.21. Check Timing
2.5.22. Report SDC
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2.5.21. Check Timing
The Timing Analyzer's Reports > Constraint Diagnostics > Check Timing command (check_timing) checks your design and constraint files for problems with design constraints.
Check Timing can perform a series of different checks based on the variables and options that you specify for the command. When using scripted methods, use the -include option to specify which checks to perform. You must run Update Timing Netlist (update_timing_netlist) before running Check Timing (check_timing).
Figure 188. Check Timing Report and No Output Delay Subreport
Check Timing can report the following data:
Check Timing Data | Description |
---|---|
no_clock | Reports the registers that do not have at least one clock assignment at their clock pin, including any PLLs without a clock assignment. |
multiple_clock | Reports the registers that have more than one clock at their clock pin. If multiple clocks reach a register clock pin, you must define which clock is used for analysis. |
generated_clock | Reports the generated clocks that are invalid. Generated clocks must have a source that is triggered by a valid clock. |
no_input_delay | Reports the input ports that are not clocks that have no input delay constraint. |
no_output_delay | Reports the output ports that have no output delay constraint. |
partial_input_delay | Reports the input delays that lack a rise-min, fall-min, rise-max, and fall-max constraint set. |
partial_output_delay | Reports the output delays that lack a rise-min, fall-min, rise-max, and fall-max constraint set. |
io_min_max_delay_consistency | Reports the minimum delay values that you specify in set_input_delay or set_output_delay constraints that are not less than maximum delay values. |
reference_pin | Reports the reference pins that you specify with set_input_delay and set_output_delay using the -reference_pin that are invalid. A reference_pin is only valid if the -clock option in the same set_input_delay or set_output_delay command matches the clock that is in the direct fan-in of the reference_pin. Being in the direct fan-in of the reference_pin means that there must be no keepers between the clock and the reference_pin. |
latency_override | Reports the instances where the clock latency that you set on a port or pin overrides the more generic clock latency set on a clock. You can set clock latency on a clock, where the latency applies to all keepers clocked by the clock. You can also set clock latency on a port or pin, where the latency applies to registers in the fan-out of the port or pin. |
loops | Reports the instances where there are strongly connected components in the netlist. These loops prevent a design from properly analysis. The loops check also reports whether loops exist but are marked so that they are not traversed by timing analysis. |
latches | Reports the instances where latches are present in the design and warns that latches may not be analyzed properly. For best results, change your design to remove latches whenever possible. |
pos_neg_clock_domain | Reports the instances where any register is clocked by both the rising and falling edges of the same clock. If this scenario is necessary, such as in a clock multiplexer, create two separate clocks that have similar settings and are assigned to the same node. |
pll_cross_check | Reports the instances where clocks that are assigned to a PLL do not correspond properly with the PLL settings you define in design files. The subreport specifies the inconsistent settings, or an unmatched number of clocks associated with the PLL. |
uncertainty | Reports the clock-to-clock transfers that do not have a clock uncertainty assignment set between the two clocks. If the target device family has derive_clock_uncertainty support, this report also includes the number of user-defined set_clock_uncertainty assignments that have less than recommended clock uncertainty value. |
virtual_clock | Reports the unreferenced virtual clocks without constraint. |
partial_multicycle | Reports the setup multicycle assignments without a corresponding hold multicycle assignment, and whether each hold muticycle assignment has a corresponding setup multicycle assignment. |
multicycle_consistency | Reports the multicycle instances where a setup multicycle does not equal one less than the hold multicycle. Appropriate Hold multicycle assignments are usually one cycle less than setup multicycle assignments. |
partial_min_max_delay | Reports the minimum delay assignments without a corresponding maximum delay assignment, and vice versa. |
clock_assignments_on_output_ports | Reports the output ports that have clock assignments. |
input_delay_assigned_to_clock | Reports the clocks with input delay values set. The Timing Analyzer ignores input delays set on clock ports because clock-as-data analysis takes precedence. |
internal_io_delay | Reports the I/O delay constraints that have no specification for -reference_pin and -source_latency_included, and where -clock is a clock that is not assigned to a top level input or output port. |