ASMI Parallel Intel® FPGA IP Core User Guide

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ID 683205
Date 7/02/2019
Public
Document Table of Contents
Document Table of Contents x
1. ASMI Parallel Intel® FPGA IP Core User Guide
1. ASMI Parallel Intel® FPGA IP Core User Guide x
1.1. Device Family Support 1.2. Ports and Parameters 1.3. Installing and Licensing Intel® FPGA IP Cores 1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements 1.5. ASMI Parallel Intel® FPGA IP Core User Guide Archives 1.6. Document Revision History for ASMI Parallel Intel® FPGA IP Core User Guide
1.2. Ports and Parameters x
1.2.1. Parameters 1.2.2. Input Ports 1.2.3. Output Ports
1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements x
1.4.1. Read Memory Capacity ID from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.2. Read Silicon ID from the EPCS Device 1.4.3. Protect a Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.4. Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.7. Read Status Register of the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.8. Erase Memory in a Specified Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.9. Erase Memory in Bulk on the EPCS/EPCQ/EPCQ-L256/EPCQ-A Device 1.4.10. Erase Memory in a Specified Die on the EPCQ-L512 and EPCQ-L1024 Device 1.4.11. Enable 4-byte Addressing Operation for an EPCQ256/EPCQ-L256 or Larger Devices 1.4.12. 4-byte Addressing Exit Operation for an EPCQ256/EPCQ-L256 or Larger Devices
1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.5.1. EPCQ/EPCQ-L/EPCQ-A Devices Extended SPI Dual and Quad I/O Instruction 1.4.5.2. EPCQ/EPCQ-L/EPCQ-A Devices Read Dummy Clock Instruction
1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.6.1. Single-Byte Write Operation 1.4.6.2. Page-Write Operation
1. ASMI Parallel Intel® FPGA IP Core User Guide

1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements

Understanding the operations help you to implement the ASMI Parallel Intel® FPGA IP core with the functions you desire.

The following shows the supported operations listed from the highest priority to the lowest. The IP core executes the operation with the highest priority when more than one operation are requested at once. The rest is ignored.

  • Read Memory Capacity ID from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
  • Read Silicon ID from the EPCS Device
  • Protect a Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
  • Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
  • Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
  • Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
  • Read Status Register of the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
  • Erase Memory in a Specified Sector on the EPCS/EPCQ/EPCQ-L256/EPCQ-A Device
  • Erase Memory in Bulk on the EPCS/EPCQ/EPCQ-L256/EPCQ-A Device
  • Erase Memory in Specified Die on EPCQ-L512 and EPCQ-L1024
  • Enable 4-byte Addressing Operation for an EPCQ256/EPCQ-L256 or larger devices
  • 4-byte Addressing Exit Operation for an EPCQ256/EPCQ-L256 or larger devices
Note: The timing diagrams show the expected results in the hardware and are not the actual results from the simulation.

The general timing requirement for all operations is the clkin signal must toggle at the appropriate frequency range at all times. The IP core uses the clkin signal to feed the EPCS/EPCQ/EPCQ-L/EPCQ-A device and to perform internal processing. For a read operation, the clkin signal can toggle at a maximum frequency of 20 MHz. For a fast read operation, the clkin signal can toggle at a maximum frequency of 25 MHz. Even though the flash device data sheets may show a higher clock rate, due to FPGA and board delays the ASMI Parallel Intel® FPGA IP core clkin should not exceed these rates.

Note: Intel® recommends that you check the busy signal before sending a new command. When the busy signal is deasserted, allow two clock cycles before sending a new signal. This delay allows the circuit to reset itself before executing the next command.

Section Content
Read Memory Capacity ID from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
Read Silicon ID from the EPCS Device
Protect a Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
Read Status Register of the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
Erase Memory in a Specified Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
Erase Memory in Bulk on the EPCS/EPCQ/EPCQ-L256/EPCQ-A Device
Erase Memory in a Specified Die on the EPCQ-L512 and EPCQ-L1024 Device
Enable 4-byte Addressing Operation for an EPCQ256/EPCQ-L256 or Larger Devices
4-byte Addressing Exit Operation for an EPCQ256/EPCQ-L256 or Larger Devices

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