ASMI Parallel Intel® FPGA IP Core User Guide

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ID 683205
Date 7/02/2019
Public
Document Table of Contents
Document Table of Contents x
1. ASMI Parallel Intel® FPGA IP Core User Guide
1. ASMI Parallel Intel® FPGA IP Core User Guide x
1.1. Device Family Support 1.2. Ports and Parameters 1.3. Installing and Licensing Intel® FPGA IP Cores 1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements 1.5. ASMI Parallel Intel® FPGA IP Core User Guide Archives 1.6. Document Revision History for ASMI Parallel Intel® FPGA IP Core User Guide
1.2. Ports and Parameters x
1.2.1. Parameters 1.2.2. Input Ports 1.2.3. Output Ports
1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements x
1.4.1. Read Memory Capacity ID from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.2. Read Silicon ID from the EPCS Device 1.4.3. Protect a Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.4. Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.7. Read Status Register of the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.8. Erase Memory in a Specified Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.9. Erase Memory in Bulk on the EPCS/EPCQ/EPCQ-L256/EPCQ-A Device 1.4.10. Erase Memory in a Specified Die on the EPCQ-L512 and EPCQ-L1024 Device 1.4.11. Enable 4-byte Addressing Operation for an EPCQ256/EPCQ-L256 or Larger Devices 1.4.12. 4-byte Addressing Exit Operation for an EPCQ256/EPCQ-L256 or Larger Devices
1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.5.1. EPCQ/EPCQ-L/EPCQ-A Devices Extended SPI Dual and Quad I/O Instruction 1.4.5.2. EPCQ/EPCQ-L/EPCQ-A Devices Read Dummy Clock Instruction
1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.6.1. Single-Byte Write Operation 1.4.6.2. Page-Write Operation
1. ASMI Parallel Intel® FPGA IP Core User Guide

1.2.3. Output Ports

This table lists the output ports for the ASMI Parallel Intel® FPGA IP core.
Table 3.  Output Ports
Port Condition Size Descriptions
asmi_dclk Optional 1 bit Provides clock signal to the EPCS/EPCQ/EPCQ-L/EPCQ-A device when you select the Disable dedicated Active Serial interface option.
asmi_scein Optional 1 or 3 bit Provides the ncs signal to the EPCS/EPCQ/EPCQ-L/EPCQ-A device when you select the Disable dedicated Active Serial interface option.

If you are using Arria 10 or Cyclone 10 GX devices, the bit size is 3.

asmi_sdoin Optional 1 or 4 bit Provides data signal to the EPCS/EPCQ/EPCQ-L/EPCQ-A device when you select the Disable dedicated Active Serial interface option.

If you are using Arria V, Cyclone V, Stratix V, Cyclone 10 GX, or Arria 10 devices, then the bit size is 4.

asmi_dataoe Optional 1 or 4 bit Provides data input/output control signal to the EPCS/EPCQ/EPCQ-L/EPCQ-A device when you the Disable dedicated Active Serial interface option.

If you are using Arria V, Cyclone V, Stratix V, Cyclone 10 GX, or Arria 10 devices, then the bit size is 4.

busy Required 1 bit Indicates the IP core is performing a valid operation. The busy signal goes high when the IP core is executing a valid operation, and goes low after the operation.

When the busy signal is deasserted, allow two clock cycles before sending a new signal. This delay allows the circuit to reset itself before executing the next command.

data_valid Required 1 bit Indicates that the dataout[7..0] port contains a valid data byte read from the EPCS/EPCQ/EPCQ-L/EPCQ-A memory. Sample the dataout[7..0]port only when the data_valid signal is high.
dataout[] Required 8 bit Contains the data byte read from the EPCS/EPCQ/EPCQ-L/EPCQ-A memory during read operation. This port holds the value of the last data byte read until the device resets, or until the IP core carries out a new read operation. Sample the dataout[7..0] port only when the data_valid signal is high.
epcs_id[] Optional 8 bit Contains the silicon ID of the EPCS device after the read silicon ID operation. This port holds the value of the silicon ID until the device resets. Sample the epcs_id[7..0] port after the busy signal goes low.
illegal_erase Optional 1 bit Indicates that an erase instruction has been set to a protected sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A memory. This port is required when you specify the sector_erase port, bulk_erase port, or die_erase port. The illegal_erase signal goes high to indicate that the IP core has canceled the erase instruction. The signal pulses high for two clock cycles—one clock cycle before, and one clock cycle after the busy signal goes low. Monitor this port to detect the status of an erase operation.
illegal_write Optional 1 bit Indicates that a write instruction is targeting a protected sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A memory. This port is required when you specify the write port. The illegal_write signal goes high to indicate that the IP core has canceled a write instruction. The signal pulses high for two clock cycles—one clock cycle before, and one clock cycle after the busy signal goes low. Monitor this port to detect the status of a write operation.
rdid_out[] Optional 8 bit Contains the memory capacity ID of the EPCS/EPCQ/EPCQ-L/EPCQ-A device after the read memory capacity ID operation is completed. This port holds the value until the device resets. Sample the rdid_out[7..0] port after the busy signal goes low.
read_address[] Optional 24 or 32 bit Contains the memory address of the EPCS/EPCQ/EPCQ-L/EPCQ-A to be read from. Use this port together with the dataout[7..0]port.

For EPCQ256/EPCQ-L256 or larger devices, the width of the addr and read_address signals is 32 bit.

status_out[] Optional 8 bit Contains the value of the EPCS/EPCQ/EPCQ-L/EPCQ-A status register after the read status register operation is completed. This port holds the value until you execute another reading status register operation, or until you reset the device. To obtain the most recent value of the status register, you must perform a read status register operation before sampling the status_out[7..0] port. Sample the port only after the busy signal goes low.
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