ASMI Parallel Intel® FPGA IP Core User Guide

ID 683205
Date 7/02/2019
Public
Document Table of Contents

1.4.1. Read Memory Capacity ID from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device

Use the read_rdid signal to instruct the IP core to read the memory capacity ID from the EPCS/EPCQ/EPCQ-L/EPCQ-A device.
Figure 4. Reading Memory Capacity IDThis figure shows an example of the latency when the ASMI Parallel Intel® FPGA IP core is executing the read command. The latency shown does not correctly indicate the true processing time. The latency only shows the command.
Note: When the busy signal is deasserted, allow two clock cycles before sending a new signal. This delay allows the circuit to reset itself before executing the next command.


The IP core registers the read_rdid signal on the rising edge of the clkin signal. After the IP core registers the read_rdid signal, the IP core asserts the busy signal to indicate that the read command is in progress.

Ensure that the memory capacity ID appears on the rdid_out[7..0] signal before the busy signal is deasserted. This allows you to sample the rdid_out[7..0] signal as soon as the busy signal is deasserted.

The rdid_out[7..0] signal holds the value of the memory capacity ID until the device resets. Therefore, you must execute this read command only once.

Note: To meet setup and hold time requirements, assert the read_rdid signal any time between the rising edges of the clkin signal, and keep the read_rdid signal asserted for at least one full clock cycle. Ensure that the read_rdid signal assertion does not coincide with the rising edges of the clkin signal.

If you keep the read_rdid signal asserted while the busy signal is deasserted after the IP core has finished processing the read command, the IP core re-registers the read_rdid signal as a value of one and carries out the command again. Therefore, you must deassert the read_rdid signal before the busy signal is deasserted.