Visible to Intel only — GUID: sam1412044643710
Ixiasoft
1.1. Device Family Support
1.2. Ports and Parameters
1.3. Installing and Licensing Intel® FPGA IP Cores
1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements
1.5. ASMI Parallel Intel® FPGA IP Core User Guide Archives
1.6. Document Revision History for ASMI Parallel Intel® FPGA IP Core User Guide
1.4.1. Read Memory Capacity ID from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
1.4.2. Read Silicon ID from the EPCS Device
1.4.3. Protect a Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
1.4.4. Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
1.4.7. Read Status Register of the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
1.4.8. Erase Memory in a Specified Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
1.4.9. Erase Memory in Bulk on the EPCS/EPCQ/EPCQ-L256/EPCQ-A Device
1.4.10. Erase Memory in a Specified Die on the EPCQ-L512 and EPCQ-L1024 Device
1.4.11. Enable 4-byte Addressing Operation for an EPCQ256/EPCQ-L256 or Larger Devices
1.4.12. 4-byte Addressing Exit Operation for an EPCQ256/EPCQ-L256 or Larger Devices
Visible to Intel only — GUID: sam1412044643710
Ixiasoft
1.4.12. 4-byte Addressing Exit Operation for an EPCQ256/EPCQ-L256 or Larger Devices
The ex4b_addr input port allow you to exit the 4-byte addressing operation. These input ports are available when you use an EPCQ256/EPCQ-L256 or larger devices.
Note: The 4-byte addressing exit operation is supported for EPCQ256/EPCQ-L256 or larger devices only, so you must enable 4-byte addressing when you use an EPCQ256/EPCQ-L256 or larger devices.
To exit 4-byte addressing mode, pull the wren signal high, followed by at least one clock cycle. If wren signal is zero, the 4-byte addressing mode exit operation will not be carried out even though the ex4b_addr is high. After the IP core receives the command, the IP core asserts the busy signal to indicate that the exit operation is in progress.