ASMI Parallel Intel® FPGA IP Core User Guide

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ID 683205
Date 7/02/2019
Public
Document Table of Contents
Document Table of Contents x
1. ASMI Parallel Intel® FPGA IP Core User Guide
1. ASMI Parallel Intel® FPGA IP Core User Guide x
1.1. Device Family Support 1.2. Ports and Parameters 1.3. Installing and Licensing Intel® FPGA IP Cores 1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements 1.5. ASMI Parallel Intel® FPGA IP Core User Guide Archives 1.6. Document Revision History for ASMI Parallel Intel® FPGA IP Core User Guide
1.2. Ports and Parameters x
1.2.1. Parameters 1.2.2. Input Ports 1.2.3. Output Ports
1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements x
1.4.1. Read Memory Capacity ID from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.2. Read Silicon ID from the EPCS Device 1.4.3. Protect a Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.4. Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.7. Read Status Register of the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.8. Erase Memory in a Specified Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.9. Erase Memory in Bulk on the EPCS/EPCQ/EPCQ-L256/EPCQ-A Device 1.4.10. Erase Memory in a Specified Die on the EPCQ-L512 and EPCQ-L1024 Device 1.4.11. Enable 4-byte Addressing Operation for an EPCQ256/EPCQ-L256 or Larger Devices 1.4.12. 4-byte Addressing Exit Operation for an EPCQ256/EPCQ-L256 or Larger Devices
1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.5.1. EPCQ/EPCQ-L/EPCQ-A Devices Extended SPI Dual and Quad I/O Instruction 1.4.5.2. EPCQ/EPCQ-L/EPCQ-A Devices Read Dummy Clock Instruction
1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.6.1. Single-Byte Write Operation 1.4.6.2. Page-Write Operation
1. ASMI Parallel Intel® FPGA IP Core User Guide

1.4.10. Erase Memory in a Specified Die on the EPCQ-L512 and EPCQ-L1024 Device

Use the die_erase signal to instruct the IP core to erase memory in a specified die on the EPCQ-L512 or EPCQ-L1024 device.
Figure 18. Erasing Memory in a Specified DieThis figure shows an example of the latency when the ASMI Parallel Intel® FPGA IP core is executing the erase memory command. The latency shown does not correctly reflect the true processing time. It shows the command only.
Note: When the busy signal is deasserted, allow two clock cycles before sending a new signal. This delay allows the circuit to reset itself before executing the next command.

The IP core registers the die_erase signal on the rising edge of the clkin signal. The address placed on the addr[31..0] signal is a valid address in the die that you can erase.

Ensure that the memory address to be erased appears on the addr[31..0] signal before setting the wren and die_erase signals to a value of one. After the IP core receives the die erase command, the IP core asserts the busy signal when erasing the die.

If wren signal has a value of zero, then the die erase operation is carried out, and the busy signal remains deasserted.

If the memory region is protected (specified in the EPCQ-L status register), the erase operation cannot proceed, and the busy signal is deasserted. The illegal_erase port is then asserted for two clock cycles to indicate that the erase operation has been canceled.

If you keep the wren and die_erase signals asserted while the busy signal is deasserted after the IP core has finished erasing the memory, the IP core re-registers the wren and die_erase signals as a value of one and carries out another die erase operation. Therefore, before the IP core deasserts the busy signal, you must deassert the wren and die_erase signals.

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