1.4.6.2. Page-Write Operation
The IP core executes the page-write sequence in two stages: stage 1 and stage 2.
For stage 1, you must assert the wren and shift_bytes signals to enable the IP core to sample the data byte at datain[7..0]signal and to store the byte internally in the page-write buffer. The IP core samples datain[7..0]signal at the rising edge of the clkin signal.
You do not need to ensure that a new data byte is available with each clock cycle; however, you can use the shift_bytes signal to control when the IP core takes in a new data byte. Every time a new data byte is ready at datain[7..0] signal, assert the shift_bytes signal for one clock cycle to enable the IP core to sample the data. Set the wren signal to a value of one.
Continue controlling the shift_bytes and wren signals until the entire data bytes shift into the page-write buffer for writing.
You can write any number of data bytes less than the PAGE_SIZE parameter value set in the IP parameter editor.
For stage 2, you must ensure that the start memory address to be written appears on the addr[23..0] signal before you assert the write signal. When you have completed sending all data bytes, assert the write signal to indicate to the IP core that the internal write can proceed. The IP core registers both the write and addr[23..0] ports on the rising edge of the clkin signal. You need to only send the start memory address to be written to. The EPCS/EPCQ/EPCQ-L/EPCQ-A device treats the address increment internally.
The IP core passes the data that you supply and the memory address as it is to the EPCS/EPCQ/EPCQ-L/EPCQ-A device. To avoid unexpected rearrangement of data order by the EPCS/EPCQ/EPCQ-L/EPCQ-A write operation, use a PAGE_SIZE of 256 bytes, and execute page-write operations at the start of each page boundary (where the addr[7..0] bits are all 0).
The IP core asserts the busy signal after receiving the write command.
The busy signal remains asserted while the EPCS/EPCQ/EPCQ-L/EPCQ-A device is writing into the memory.
If the wren signal has a value of zero, the IP core will not carry out the write operation, and the busy signal remains deasserted.
If the memory region is protected (you can set this in the EPCS/EPCQ/EPCQ-L/EPCQ-A status register), the write operation does not proceed, and the busy signal is deasserted. The IP core then asserts the illegal_write signal for two clock cycles to indicate that the write operation has been canceled.
If you keep both the wren and write signals asserted while the busy signal is deasserted after the IP core has finished processing the write command, the IP core re-registers the wren and write signals as a value of one, and carries out another write command. Therefore, before the IP core deasserts the busy signal, you must deassert the wren and write signals.