ASMI Parallel Intel® FPGA IP Core User Guide

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ID 683205
Date 7/02/2019
Public
Document Table of Contents
Document Table of Contents x
1. ASMI Parallel Intel® FPGA IP Core User Guide
1. ASMI Parallel Intel® FPGA IP Core User Guide x
1.1. Device Family Support 1.2. Ports and Parameters 1.3. Installing and Licensing Intel® FPGA IP Cores 1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements 1.5. ASMI Parallel Intel® FPGA IP Core User Guide Archives 1.6. Document Revision History for ASMI Parallel Intel® FPGA IP Core User Guide
1.2. Ports and Parameters x
1.2.1. Parameters 1.2.2. Input Ports 1.2.3. Output Ports
1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements x
1.4.1. Read Memory Capacity ID from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.2. Read Silicon ID from the EPCS Device 1.4.3. Protect a Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.4. Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.7. Read Status Register of the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.8. Erase Memory in a Specified Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.9. Erase Memory in Bulk on the EPCS/EPCQ/EPCQ-L256/EPCQ-A Device 1.4.10. Erase Memory in a Specified Die on the EPCQ-L512 and EPCQ-L1024 Device 1.4.11. Enable 4-byte Addressing Operation for an EPCQ256/EPCQ-L256 or Larger Devices 1.4.12. 4-byte Addressing Exit Operation for an EPCQ256/EPCQ-L256 or Larger Devices
1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.5.1. EPCQ/EPCQ-L/EPCQ-A Devices Extended SPI Dual and Quad I/O Instruction 1.4.5.2. EPCQ/EPCQ-L/EPCQ-A Devices Read Dummy Clock Instruction
1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.6.1. Single-Byte Write Operation 1.4.6.2. Page-Write Operation
1. ASMI Parallel Intel® FPGA IP Core User Guide

1.4.2. Read Silicon ID from the EPCS Device

Use the read_sid signal to instruct the IP core to read the silicon ID from the EPCS device.
Figure 5. Reading Silicon IDThis figure shows an example of the latency when the ASMI Parallel Intel® FPGA IP core is executing the read command. The latency shown does not correctly indicate the true processing time. The latency only shows the command.
Note: When the busy signal is deasserted, allow two clock cycles before sending a new signal. This delay allows the circuit to reset itself before executing the next command.


The IP core registers the read_sid signal on the rising edge of the clkin signal. After the IP core registers the read_sid signal, it asserts the busy signal to indicate that the read command is in progress.

Ensure that the silicon ID appears on the epcs_id[7..0] signal before the busy signal is deasserted. Therefore, you can sample the epcs_id[7..0] signal as soon as the busy signal is deasserted.

The epcs_id[7..0] signal holds the value of the silicon ID until the device resets. Therefore, you must execute this command only once.

Note: To meet setup and hold time requirements, assert the read_sid signal any time between the rising edges of the clkin signal, and keep the read_sid signal asserted for at least one full clock cycle. Ensure that the read_sid signal assertion does not coincide with the rising edges of the clkin signal.

If you keep the read_sid signal asserted while busy signal is deasserted and the IP core has finished processing the read command, the IP core re-registers the read_sid signal as a value of one and carries out another read command. Therefore, before the IP core deasserts the busy signal, you must deassert the read_sid signal.

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