Arria GX,

Arria II GX,

Arria II GZ,

Arria® V,

Arria® V GZ,

Cyclone,

Cyclone II,

Cyclone III,

Cyclone III LS,

Cyclone IV GX,

Cyclone IV E,

Cyclone® V,

HardCopy III,

HardCopy IV,

Stratix II,

Stratix II GX,

Stratix III,

Stratix IV,

Stratix® V,

Intel® Arria® 10,

Intel® Cyclone® 10 LP,

Intel® Cyclone® 10 GX,

• Specifies the device family you intend to use. Use this parameter for modeling and behavioral simulation purposes, as each device family has its own ASMI primitive.

EPCS1,

EPCS4,

EPCS16,

EPCS64,

EPCS128,

EPCQ16,

EPCQ32,

EPCQ64,

EPCQ128,

EPCQ256,

EPCQ512,

EPCQ-L256,

EPCQ-L512,

EPCQ-L1024,

EPCQ4A,

EPCQ16A,

EPCQ32A,

EPCQ64A,

EPCQ128A,

• Specify the EPCS/EPCQ/EPCQ-L/EPCQ-A type you want to use.
• The default value is EPCS4.

• Enables the ability to read the silicon ID of the EPCS device with an active-high read_sid input signal. When this signal is asserted, the IP core reads the silicon ID of the EPCS device. After reading the silicon ID, the 8-bit silicon ID appears on the epcs_id[7..0]signal until the device resets.
• This option is available only for EPCS1, EPCS4, EPCS16, and EPCS64 devices.

• Enables the ability to read the memory capacity ID of the EPCS/EPCQ/EPCQ-L/EPCQ-A device with an active-high input signal named read_rdid. When this signal is asserted, the IP core reads the memory capacity ID of the EPCS/EPCQ/EPCQ-L/EPCQ-A device. The 8-bit ID appears on the rdid_out[7..0]signal until the device resets.
• This option is available for all devices, except for EPCS1 and EPCS4.

• Enables the ability to read the port status using an active-high input signal named read_status. When this signal is asserted, the IP core reads the EPCS/EPCQ/EPCQ-L/EPCQ-A status register. As the status register is read, the 8-bit value appears on the status_out[7..0]signal.
• This option is available for all EPCS/EPCQ/EPCQ-L/EPCQ-A devices.

• This signal holds the address from which data is being read. This signal works together with the dataout[7..0]signal. As data appears on dataout[7..0], the address from which the data byte was read appears on the read-address output port. For EPCQ256/EPCQ-L256 or larger devices, the width of the addr and read_address signals is 32 bit. For other devices, the width of the addr and read_address signals is 24 bit.
• This option is available for all EPCS/EPCQ/EPCQ-L/EPCQ-A devices.

• Enables the ability to perform a fast read operation with an active-high input signal named fast_read. When this signal is asserted, the IP core performs a fast read from the memory address that appears on the addr[23..0]signal. Each data byte appears on the dataout[7..0] signal as it is read. For EPCQ256/EPCQ-L256 or larger devices, the width of the addr and read_address signals is 32 bit.
• The fast_read signal supports single-byte fast read and sequential fast read. If a write or erase operation is in progress (the busy signal is asserted), the fast read command is ignored. The fast read operation occurs only when allowed by the rden signal.
• This option is available for all EPCS/EPCQ/EPCQ-L/EPCQ-A devices, except for EPCS1 and EPCS4 devices.The fast read operation replaces the normal settings.

• The following commands are the instructions from the EPCQ/EPCQ-L extended serial peripheral interface (SPI) protocol which uses multiple data lines:

  Dual Fast Read (Dual Input/Output Fast Read)

  Quad Fast Read (Quad Input/Output Fast Read)

  Dual Write (Dual Input Extended Fast Program)

  Quad Write (Quad Input Extended Fast Program)

• These commands are combined into the following ports:

  Fast read port – fast read (x1), dual fast read and quad fast read

  Write port – write (x1), dual write and quad write

• You can choose which I/O mode to use, the choices are Standard (x1), Dual (x2) or Quad (x4) mode.
• This option is only available for EPCQ/EPCQ-L devices.
• EPCQ-A devices do not support Quad Write.

• This option is disabled by default and the IP core generates the design file as per usual.
• To perform fast read operation, align the dummy cycles of EPCQ/EPCQ-L devices with ASMI Parallel Intel® FPGA IP core designated value.
• When enabling this option, the read_dummyclk input pin is created. Connect this pin to low. The ASMI Parallel Intel® FPGA IP core reads the dummy clock stored in a non-volatile configuration register of a flash at the beginning of the operation. Do not assert the signal to high.
• This option is available for EPCQ/EPCQ-L devices only.

• Enables the ability to write to the EPCS/EPCQ/EPCQ-L/EPCQ-A device with an active-high input signal named write. When this port is asserted, the IP core writes the data from the datain[7..0]signal (for single-byte write) or from the page-write buffer (for page-write) to the address that appears on the addr[23..0]port, and to subsequent addresses for page-write. For EPCQ256/EPCQ-L256 or larger devices, the width of the addr and read_address signals is 32 bit.
• In page-write mode, you must use the shift_byte signal to shift in data bytes before asserting the write signal.
• This option is available for all EPCS/EPCQ/EPCQ-L/EPCQ-A devices.

• Enables write and erase operations to the EPCS/EPCQ/EPCQ-L/EPCQ-A memory with an active-high input signal named wren. If this signal is asserted, the write and erase operations are enabled, and disabled if the signal is deasserted. If you are not using the wren signal, all write and erase operations are automatically enabled when the command appears on the relevant IP core input port. The affected commands are write, sector protect, bulk erase, and sector erase.
• This option is only available when you turn on the Enable write operation, Use ‘sector protect’ port or die erase port, Use ‘bulk erase’ port, or Use ‘sector erase’ port option.
• This option is available for all EPCS/EPCQ/EPCQ-L/EPCQ-A devices.

• Enables the ability to erase the entire memory of the EPCS/EPCQ/EPCQ-L256/EPCQ-A device, including the configuration data portion with an active-high input signal named bulk_erase. When this signal is asserted, the IP core implements a full erase that sets the entire memory bits of the EPCS/EPCQ/EPCQ-L256/EPCQ-A device to a value of one.
• This option is available for all EPCS/EPCQ/EPCQ-A devices.

• Enables the ability to erase a certain sector in the EPCS/EPCQ/EPCQ-A memory with an active-high input signal named sector_erase. When the signal is asserted, the IP core implements a full erase of the sector. The value of the addr[23..0]signal indicates the sector to erase. For EPCQ256/EPCQ-L256 or larger devices, the width of the addr and read_address signals is 32 bit.
• This option is available for all EPCS/EPCQ/EPCQ-L/EPCQ-A devices.

• Enables the ability to protect sectors in the EPCS/EPCQ/EPCQ-L/EPCQ-A device from write and erase operations with an active-high input port named sector_protect. When this port is asserted, the IP core reads the block protection code value on the datain[7..0]signal and writes it to the EPCS/EPCQ/EPCQ-L/EPCQ-A status register. To protect specific memory sectors, you must send their block protection code to the datain[7..0] signal.
• This option is available for all EPCS/EPCQ/EPCQ-L/EPCQ-A devices.

• To exit the 4-byte addressing mode when you use an EPCQ256/EPCQ-L256 or larger devices, pull the WREN signal high, followed by at least one clock cycle. If WREN signal is zero, the 4-byte addressing mode exit operation will not be carried out even though the ex4b_addr is high. After the IP core receives the command, the IP core asserts the busy signal to indicate that the exit operation is in progress.
• Only applicable for EPCQ256/EPCQ-L256 or larger devices.

• This option is disabled by default and the IP core generates the design file as per usual.
• The ASMI Parallel Intel® FPGA IP core instantiates the ASMI block internally and connects to the block automatically.
• The IP core creates the following input/output pins when you enable this option:

  asmi_dataout,

  asmi_dclk,

  asmi_scein,

  asmi_sdoin,

  asmi_dataoe.

• When you enable this option, the ASMI Parallel Intel® FPGA IP core will not instantiate ASMI block automatically, and all signals to interface with ASMI block are routed to the top level of your design. You must then instantiate the ASMI block externally, and assign the ASMI ports in the ASMI Parallel Intel® FPGA IP core to the dedicated pins location.
• The CLI parameter to disable this option is USE_ASMIBLOCK=ON.
• This option is available for all EPCS/EPCQ/EPCQ-L/EPCQ-A devices.