ASMI Parallel Intel® FPGA IP Core User Guide

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ID 683205
Date 7/02/2019
Public
Document Table of Contents
Document Table of Contents x
1. ASMI Parallel Intel® FPGA IP Core User Guide
1. ASMI Parallel Intel® FPGA IP Core User Guide x
1.1. Device Family Support 1.2. Ports and Parameters 1.3. Installing and Licensing Intel® FPGA IP Cores 1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements 1.5. ASMI Parallel Intel® FPGA IP Core User Guide Archives 1.6. Document Revision History for ASMI Parallel Intel® FPGA IP Core User Guide
1.2. Ports and Parameters x
1.2.1. Parameters 1.2.2. Input Ports 1.2.3. Output Ports
1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements x
1.4.1. Read Memory Capacity ID from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.2. Read Silicon ID from the EPCS Device 1.4.3. Protect a Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.4. Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.7. Read Status Register of the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.8. Erase Memory in a Specified Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.9. Erase Memory in Bulk on the EPCS/EPCQ/EPCQ-L256/EPCQ-A Device 1.4.10. Erase Memory in a Specified Die on the EPCQ-L512 and EPCQ-L1024 Device 1.4.11. Enable 4-byte Addressing Operation for an EPCQ256/EPCQ-L256 or Larger Devices 1.4.12. 4-byte Addressing Exit Operation for an EPCQ256/EPCQ-L256 or Larger Devices
1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.5.1. EPCQ/EPCQ-L/EPCQ-A Devices Extended SPI Dual and Quad I/O Instruction 1.4.5.2. EPCQ/EPCQ-L/EPCQ-A Devices Read Dummy Clock Instruction
1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.6.1. Single-Byte Write Operation 1.4.6.2. Page-Write Operation
1. ASMI Parallel Intel® FPGA IP Core User Guide

1.4.3. Protect a Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device

Use the sector_protect signal to instruct the IP core to protect a sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A device.
Figure 6. Protecting a SectorThis figure shows an example of the latency when the ASMI Parallel Intel® FPGA IP core is executing the sector protect command. The latency shown does not correctly reflect the true processing time. It shows the command only.
Note: When the busy signal is deasserted, allow two clock cycles before sending a new signal. This delay allows the circuit to reset itself before executing the next command.


This command writes the EPCS/EPCQ/EPCQ-L/EPCQ-A status register to set the block protection bits. The block protection bits show which sectors are protected from write or erase, and provide protection in addition to that provided by the wren signal.

You can set the block protection bits in the EPCS/EPCQ/EPCQ-L/EPCQ-A status register to protect those sectors that contain configuration data, and are not intended for general-purpose memory usage.

Ensure that the 8-bit code is available on the datain[7..0] signal before asserting the sector_protect and wren signals. The IP core registers the sector_protect signal at the positive edge of the clkin signal.

The IP core asserts the busy signal as soon as it receives the sector_protect signal. The busy signal remains asserted while the EPCS/EPCQ/EPCQ-L/EPCQ-A status register is written.

If the wren signal has a value of zero, the IP core will not carry out the sector_protect signal, and the busy signal remains deasserted.

Note: If you keep the wren and sector_protect signals asserted while the busy signal is deasserted after the IP core has finished processing the sector protect command, the IP core re-registers the wren and sector_protect signals as a value of one and carries out another write status register operation. Therefore, before the IP core deasserts the busy signal, you must deassert the sector_protect signal.

The IP core uses only bits 2 to 3, or 2 to 4 for EPCS devices, and 2 to 5, or 2 to 6 for EPCQ/EPCQ-L/EPCQ-A devices out of the 8 bits for block protection. The rest of the bits have other meanings for the ASMI operation, and cannot be overwritten by the sector protect operation. Whenever the input address is in a protected sector, the IP core omits the operation and the busy signal remains deasserted.

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