ASMI Parallel Intel® FPGA IP Core User Guide

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ID 683205
Date 7/02/2019
Public
Document Table of Contents
Document Table of Contents x
1. ASMI Parallel Intel® FPGA IP Core User Guide
1. ASMI Parallel Intel® FPGA IP Core User Guide x
1.1. Device Family Support 1.2. Ports and Parameters 1.3. Installing and Licensing Intel® FPGA IP Cores 1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements 1.5. ASMI Parallel Intel® FPGA IP Core User Guide Archives 1.6. Document Revision History for ASMI Parallel Intel® FPGA IP Core User Guide
1.2. Ports and Parameters x
1.2.1. Parameters 1.2.2. Input Ports 1.2.3. Output Ports
1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements x
1.4.1. Read Memory Capacity ID from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.2. Read Silicon ID from the EPCS Device 1.4.3. Protect a Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.4. Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.7. Read Status Register of the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.8. Erase Memory in a Specified Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.9. Erase Memory in Bulk on the EPCS/EPCQ/EPCQ-L256/EPCQ-A Device 1.4.10. Erase Memory in a Specified Die on the EPCQ-L512 and EPCQ-L1024 Device 1.4.11. Enable 4-byte Addressing Operation for an EPCQ256/EPCQ-L256 or Larger Devices 1.4.12. 4-byte Addressing Exit Operation for an EPCQ256/EPCQ-L256 or Larger Devices
1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.5.1. EPCQ/EPCQ-L/EPCQ-A Devices Extended SPI Dual and Quad I/O Instruction 1.4.5.2. EPCQ/EPCQ-L/EPCQ-A Devices Read Dummy Clock Instruction
1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.6.1. Single-Byte Write Operation 1.4.6.2. Page-Write Operation
1. ASMI Parallel Intel® FPGA IP Core User Guide

1.2.2. Input Ports

This table lists the input ports for the ASMI Parallel Intel® FPGA IP core.
Table 2.  Input Ports
Port Condition Size Descriptions
addr[] Required 24 or 32 bit Contains the value of the EPCS/EPCQ/EPCQ-L/EPCQ-A memory address to be read from, written to, and erased from.

For EPCQ256/EPCQ-L256 or larger devices, the width of the addr[] is 32 bit.

asmi_dataout[] Optional 1 bit Input port to feed data from EPCS/EPCQ/EPCQ-L/EPCQ-A device if select the Disable dedicated Active Serial interface option.

If you are using Arria® V, Cyclone® V, Stratix® V, Intel® Arria® 10, or Intel® Cyclone® 10 GX devices, then the bit size is 4 bit.

bulk_erase Optional 1 bit

Active-high port that executes the bulk erase operation. If asserted, the IP core performs a full-erase operation that sets all memory bits of the EPCS/EPCQ/EPCQ-L256/EPCQ-A device to ‘1’, which includes the general purpose memory of the EPCS/EPCQ/EPCQ-L256/EPCQ-A device.

This is only applicable for single-die configuration devices.

clkin Required 1 bit Input clock port for the ASMI block. In general, the clkin signal must toggle at the appropriate frequency range at all times. The IP core uses the signal to feed the EPCS/EPCQ/EPCQ-L/EPCQ-A device and to perform internal processing.
  • Fast read: The clock signal can toggle at a maximum frequency of 25 Mhz
  • Read: The clock signal can toggle at a maximum frequency of 20 Mhz
datain[] Optional 8 bit Parallel input data of 1-byte length for write and sector protect operations.
en4b_addr Required 1 bit When you select EPCQ256/EPCQ-L256 or larger devices as your configuration device, address width will change from 0..23 to 0..31. EPCQ256 supports Dual and Quad data width.

If you select EPCQ256/EPCQ-L256 or larger devices as your configuration device, this port is required.

ex4b_addr Optional 1 bit To exit the 4-byte addressing mode when you use an EPCQ256/EPCQ-L256 or larger devices, pull the WREN signal high, followed by at least one clock cycle. If WREN signal is zero, the 4-byte addressing mode exit operation will not be carried out even though the ex4b_addr is high. After the IP core receives the command, the IP core asserts the busy signal to indicate that the exit operation is in progress.

If you select EPCQ256/EPCQ-L256 or larger devices as your configuration device, this port is required.

fast_read Optional 1 bit Active-high port that executes the fast read operation. If asserted, the IP core performs a fast read operation from a memory address value that appears on the addr[23..0] port. For EPCQ256/EPCQ-L256 or larger devices, the width of the addr and read_address signals is 32 bit.

Use the fast_read port together with the rden port.

rden Required 1 bit Active-high port that allows read and fast read operations to be performed as long as it stays asserted. This port is only for ASMI Parallel Intel® FPGA IP core and not the configuration device.
read Required 1 bit Active-high port that executes the read operation. If asserted, the IP core performs a read operation from a memory address value that appears on the addr[23..0] port. For EPCQ256/EPCQ-L256 or larger devices, the width of the addr and read_address signals is 32 bit.

Use the read port together with the rden port. The read port is disabled if the fast_read port is used.

read_dummyclk Optional 1 bit

When you use the fast read option in EPCQ/EPCQ-L device, you must enable the device dummy clock option and connect this pin to low.

When you enable this option, the dummy clock value is read from a non-volatile register of an EPCQ/EPCQ-L device, by default.

Do not assert the signal to high.
read_rdid Optional 1 bit Active-high port that executes the read memory capacity ID operation. If asserted, the IP core proceeds to read the memory capacity ID of the EPCS/EPCQ/EPCQ-L/EPCQ-A device, and the value of the memory capacity ID appears at the rdid_out[7..0] port.
read_sid Optional 1 bit Active-high port that executes the read silicon ID operation. If asserted, the IP core proceeds to read the silicon ID of the EPCS device, and the value of the silicon ID appears at the epcs_id[7..0] port.
read_status Optional 1 bit Active-high port that executes the read EPCS/EPCQ/EPCQ-L/EPCQ-A status register operation. If asserted, the IP core reads the status register of the EPCS/EPCQ/EPCQ-L/EPCQ-A device, and outputs the value at the status_out[7..0] port. You can use the read_status port to determine which memory sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A device is read-only.
reset Required 1 bit To reset all counters and registers in the ASMI Parallel Intel® FPGA IP core (not the EPCS/EPCQ/EPCQ-L/EPCQ-A devices), pull the reset signal high for at least two clock cycles.

The reset signal is asserted regardless of busy status, hence, do not assert the reset signal whenever the ASMI Parallel Intel® FPGA IP core is running.

After asserting the reset signal, allow two clock cycles to reset the circuit before sending a new signal.

Default value of the reset port is 0.

sector_erase Optional 1 bit Active-high port that executes the sector erase operation. If asserted, the IP core starts erasing the memory sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A device based on the memory address value at the addr[23..0] port. The value is a valid memory address in the sector to be erased. For EPCQ256/EPCQ-L256 or larger devices, the width of the addr and read_address signals is 32 bit.
sector_protect Optional 1 bit Active-high port that executes the sector protect operation. If asserted, the IP core takes the value of the datain[7..0] port and writes to the EPCS/EPCQ/EPCQ-L/EPCQ-A status register. The status register contains the block protection bits that represent the memory sector to be protected.
shift_bytes Optional 1 bit Active-high port that shifts data bytes during the write operation. You must use this port together with the write port during the page-write operation. The IP core samples and shifts the data in the datain[7..0] port at the rising edge of the clkin signal, as long as the shift_bytes signal is asserted. Continue shifting the required bytes into the EPCS/EPCQ/EPCQ-L/EPCQ-A device until the IP core finishes sampling and storing the data internally.
wren Optional 1 bit Active-high port that allows write and erase operations to be performed as long as it stays asserted. If the IP core does not generate this port, the IP core automatically allows all write and erase operations. Use this port with the following ports:
  • write
  • sector_protect
  • bulk_erase
  • sector_erase
  • die_erase
write Optional 1 bit Active-high port that executes the write operation. If asserted, the IP core writes the data from the datain[7..0] port (for single-byte write), or from the page-write buffer (for page-write), to the memory address specified in the addr[23..0] port (and to the subsequent addresses for page write operation). For EPCQ256/EPCQ-L256 or larger devices, the width of the addr and read_address signals is 32 bit.

In page-write operation, you must use the shift_bytes port to shift in data bytes before asserting the write port.

sce[] Optional 3 bit Select targeted flash for desired operation by controlling FPGA nCSO[2..0] pin
  • 3'b000 (default value)/ 3'b001: select flash connected to nCSO[0]
  • 3'b010: select flash connected to nCSO [1]
  • 3'b100: select flash connected to nCSO [2]
sce[] is only available for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.
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