Visible to Intel only — GUID: sam1412044511921
Ixiasoft
Visible to Intel only — GUID: sam1412044511921
Ixiasoft
1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements
The following shows the supported operations listed from the highest priority to the lowest. The IP core executes the operation with the highest priority when more than one operation are requested at once. The rest is ignored.
- Read Memory Capacity ID from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
- Read Silicon ID from the EPCS Device
- Protect a Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
- Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
- Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
- Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
- Read Status Register of the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
- Erase Memory in a Specified Sector on the EPCS/EPCQ/EPCQ-L256/EPCQ-A Device
- Erase Memory in Bulk on the EPCS/EPCQ/EPCQ-L256/EPCQ-A Device
- Erase Memory in Specified Die on EPCQ-L512 and EPCQ-L1024
- Enable 4-byte Addressing Operation for an EPCQ256/EPCQ-L256 or larger devices
- 4-byte Addressing Exit Operation for an EPCQ256/EPCQ-L256 or larger devices
The general timing requirement for all operations is the clkin signal must toggle at the appropriate frequency range at all times. The IP core uses the clkin signal to feed the EPCS/EPCQ/EPCQ-L/EPCQ-A device and to perform internal processing. For a read operation, the clkin signal can toggle at a maximum frequency of 20 MHz. For a fast read operation, the clkin signal can toggle at a maximum frequency of 25 MHz. Even though the flash device data sheets may show a higher clock rate, due to FPGA and board delays the ASMI Parallel Intel® FPGA IP core clkin should not exceed these rates.
Section Content
Read Memory Capacity ID from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
Read Silicon ID from the EPCS Device
Protect a Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
Read Status Register of the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
Erase Memory in a Specified Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device
Erase Memory in Bulk on the EPCS/EPCQ/EPCQ-L256/EPCQ-A Device
Erase Memory in a Specified Die on the EPCQ-L512 and EPCQ-L1024 Device
Enable 4-byte Addressing Operation for an EPCQ256/EPCQ-L256 or Larger Devices
4-byte Addressing Exit Operation for an EPCQ256/EPCQ-L256 or Larger Devices