Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

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Date 11/04/2019
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Document Table of Contents x
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual x
1.1. About this Document 1.2. Introduction 1.3. CCI-P Interface 1.4. AFU Requirements 1.5. Intel® FPGA Basic Building Blocks 1.6. Device Feature List 1.7. Document Revision History for Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1.1. About this Document x
1.1.1. Intended Audience 1.1.2. Conventions 1.1.3. Related Documentation 1.1.4. Acronym List for Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual 1.1.5. Acceleration Glossary
1.2. Introduction x
1.2.1. FPGA Interface Manager (FIM) 1.2.2. Intel® FPGA Interface Unit (FIU) 1.2.3. Memory and Cache Hierarchy
1.2.2. Intel® FPGA Interface Unit (FIU) x
1.2.2.1. FIU for Intel® FPGA PAC 1.2.2.2. FIU for Intel Integrated FPGA Platform 1.2.2.3. Comparison of FIU Capabilities
1.3. CCI-P Interface x
1.3.1. Signaling Information 1.3.2. Read and Write to Main Memory 1.3.3. Interrupts 1.3.4. UMsg 1.3.5. MMIO Accesses to I/O Memory 1.3.6. CCI-P Tx Signals 1.3.7. Tx Header Format 1.3.8. CCI-P Rx Signals 1.3.9. Multi-Cache Line Memory Requests 1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) 1.3.11. Additional Control Signals 1.3.12. Protocol Flow 1.3.13. Ordering Rules 1.3.14. Timing Diagram 1.3.15. CCI-P Guidance
1.3.2. Read and Write to Main Memory x
1.3.2.1. Reading from Main Memory 1.3.2.2. Writing to Main Memory
1.3.8. CCI-P Rx Signals x
1.3.8.1. Rx Header and Rx Data Format
1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) x
1.3.10.1. Mixing Byte Enable and Full Cache Line Accesses
1.3.12. Protocol Flow x
1.3.12.1. Upstream Requests 1.3.12.2. Downstream Requests
1.3.13. Ordering Rules x
1.3.13.1. Memory Requests 1.3.13.2. MMIO Requests
1.3.13.1. Memory Requests x
1.3.13.1.1. Memory Write Fence 1.3.13.1.2. Memory Consistency Explained
1.4. AFU Requirements x
1.4.1. Mandatory AFU CSR Definitions 1.4.2. AFU Discovery Flow 1.4.3. AFU_ID
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

1.3.8. CCI-P Rx Signals

Figure 11. Rx Interface Structure Inside ccip_if_pkg.sv

There are two Rx channels:

  • Channel 0 interleaves memory responses, MMIO requests and UMsgs.
  • Channel 1 returns responses for AFU requests initiated on Tx Channel 1.

The c0TxAlmFull and c1TxAlmFull signals are inputs to the AFU. Although they are declared with the Rx signals structure, they logically belong to the Tx interface and so were described in the previous section.

Rx Channels have no flow control. The AFU must accept responses for memory requests it generated. The AFU must pre-allocate buffers before generating a memory request. The AFU must also accept MMIO requests.

Rx Channel 0 has separate valid signals for memory responses and MMIO requests. Only one of those valid signals can be set in a cycle. The MMIO request has a separate valid signal for MMIO Read and MMIO Write. When either mmioRdValid or mmioWrValid is set, the message is an MMIO request and should be processed by casting t_if_ccip_c0_Rx.hdr to t_ccip_c0_ReqMmioHdr.

Table 19.  Rx Channel Signal Description for Channel 0
Signal Width (bits) Direction Description
pck_cp2af_sRx.c0.hdr 28 Input

Channel 0 response header or MMIO request header.

Refer to Table 21.

pck_cp2af_sRx.c0.data 512 Input

Channel 0 Data bus Memory Read Response and UMsg:

  • Returns 64 bytes data

MMIO Write Request:

  • For 4 bytes write, data driven on bits [31:0]
  • For 8 bytes write, data driven on bits [63:0]
pck_cp2af_sRx.c0.rspValid 1 Input

When set to 1, it indicates header and data on Channel 0 are valid. The header must be interpreted as a memory response, decode resp_type field.

pck_cp2af_sRx.c0.mmioRdValid 1 Input

When set to 1, it indicates a MMIO Read request Channel 0.
pck_cp2af_sRx.c0.mmioWrValid 1 Input

When set to 1, it indicates a MMIO Write request on Channel 0.

Table 20.  Rx Channel Signal Description for Channel 1
Signal Width (bits) Direction Description
pck_cp2af_sRx.c1.hdr 28 Input

Channel 1 response header. Refer to Table 21

pck_cp2af_sRx.c1.rspValid 1 Input

When set to 1, it indicates header on channel 1 is a valid response.


Section Content
Rx Header and Rx Data Format

Level Two Title