Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

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Date 11/04/2019
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Document Table of Contents
Document Table of Contents x
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual x
1.1. About this Document 1.2. Introduction 1.3. CCI-P Interface 1.4. AFU Requirements 1.5. Intel® FPGA Basic Building Blocks 1.6. Device Feature List 1.7. Document Revision History for Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1.1. About this Document x
1.1.1. Intended Audience 1.1.2. Conventions 1.1.3. Related Documentation 1.1.4. Acronym List for Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual 1.1.5. Acceleration Glossary
1.2. Introduction x
1.2.1. FPGA Interface Manager (FIM) 1.2.2. Intel® FPGA Interface Unit (FIU) 1.2.3. Memory and Cache Hierarchy
1.2.2. Intel® FPGA Interface Unit (FIU) x
1.2.2.1. FIU for Intel® FPGA PAC 1.2.2.2. FIU for Intel Integrated FPGA Platform 1.2.2.3. Comparison of FIU Capabilities
1.3. CCI-P Interface x
1.3.1. Signaling Information 1.3.2. Read and Write to Main Memory 1.3.3. Interrupts 1.3.4. UMsg 1.3.5. MMIO Accesses to I/O Memory 1.3.6. CCI-P Tx Signals 1.3.7. Tx Header Format 1.3.8. CCI-P Rx Signals 1.3.9. Multi-Cache Line Memory Requests 1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) 1.3.11. Additional Control Signals 1.3.12. Protocol Flow 1.3.13. Ordering Rules 1.3.14. Timing Diagram 1.3.15. CCI-P Guidance
1.3.2. Read and Write to Main Memory x
1.3.2.1. Reading from Main Memory 1.3.2.2. Writing to Main Memory
1.3.8. CCI-P Rx Signals x
1.3.8.1. Rx Header and Rx Data Format
1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) x
1.3.10.1. Mixing Byte Enable and Full Cache Line Accesses
1.3.12. Protocol Flow x
1.3.12.1. Upstream Requests 1.3.12.2. Downstream Requests
1.3.13. Ordering Rules x
1.3.13.1. Memory Requests 1.3.13.2. MMIO Requests
1.3.13.1. Memory Requests x
1.3.13.1.1. Memory Write Fence 1.3.13.1.2. Memory Consistency Explained
1.4. AFU Requirements x
1.4.1. Mandatory AFU CSR Definitions 1.4.2. AFU Discovery Flow 1.4.3. AFU_ID
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005)

To achieve fine control of write data so that only specific bytes of data are written to host memory, use the byte enable mode. Listed below are the characteristics of byte enable memory requests:
  • Byte enable memory requests use a byte-invariant little endianness scheme. This means that:
    • For any single or multi-byte element in a data structure, the element uses the same contiguous bytes of memory, specified by the byte_start and byte_len header fields.
    • Write data is positioned in the data field at the offset where it is stored within the cache line. The first data bit written is bit byte_start*8.
  • byte_start specifies the byte index, where the least significant byte is 0 (pck_af2cp_sTx.c1.data[7:0]), and the most significant byte is 63 (pck_af2cp_sTx.c1.data[511:504])
  • byte_len specifies the number of bytes to be included in a byte-enabled memory write transaction. The byte length extends the write data towards the most significant byte.
  • Byte enable memory requests must operate with cache length (cl_len) set to 0 (a 1 CL memory write request).
  • The length cannot extend past byte 63 of pck_af2cp_sTx.c1.data. The maximum allowable byte length can be represented by the following equations:
    • If byte_start is 0:
      • MAX_BYTE_LEN = 63
    • If byte_start is not 0:
      • MAX_BYTE_LEN = 64 – byte_start
The following table is an example of how the channel 1 request header (pck_af2cp_sTx.c1.hdr) indexes bytes in byte enable mode. In this example, the AFU designer is writing bytes [20:4] (pck_af2cp_sTx.c1.data[167:32]) of the data word 0xAAAABBBBCCCCDDDDE to bytes [20:4] of the host memory at address 0xFFF00.
  Bit Index Width (bits) Field Value
Header 79:74 6 byte_len 0x11
73:72 2 vc_sel eVC_VA (0x0)
71 1 sop=1 1
70 1 (CL/byte) 0:CL, 1:byte 1
69:68 2 cl_len 0
67:64 4 req_type eREQ_WRLINE_I (0x0)
63:58 6 byte_start 0x4
57:18 40 address 0xFFF00
17:16 2 — 0x0
15:0 16 mdata 0x0
Data — 512 Data 0xAAAABBBBCCCCDDDDE
Figure 15. Host memory at address 0xFFF00. This figure shows the value in host memory before and after a write.

Section Content
Mixing Byte Enable and Full Cache Line Accesses

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