Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

Download PDF
ID 683193
Date 11/04/2019
Public
Document Table of Contents
Document Table of Contents x
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual x
1.1. About this Document 1.2. Introduction 1.3. CCI-P Interface 1.4. AFU Requirements 1.5. Intel® FPGA Basic Building Blocks 1.6. Device Feature List 1.7. Document Revision History for Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1.1. About this Document x
1.1.1. Intended Audience 1.1.2. Conventions 1.1.3. Related Documentation 1.1.4. Acronym List for Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual 1.1.5. Acceleration Glossary
1.2. Introduction x
1.2.1. FPGA Interface Manager (FIM) 1.2.2. Intel® FPGA Interface Unit (FIU) 1.2.3. Memory and Cache Hierarchy
1.2.2. Intel® FPGA Interface Unit (FIU) x
1.2.2.1. FIU for Intel® FPGA PAC 1.2.2.2. FIU for Intel Integrated FPGA Platform 1.2.2.3. Comparison of FIU Capabilities
1.3. CCI-P Interface x
1.3.1. Signaling Information 1.3.2. Read and Write to Main Memory 1.3.3. Interrupts 1.3.4. UMsg 1.3.5. MMIO Accesses to I/O Memory 1.3.6. CCI-P Tx Signals 1.3.7. Tx Header Format 1.3.8. CCI-P Rx Signals 1.3.9. Multi-Cache Line Memory Requests 1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) 1.3.11. Additional Control Signals 1.3.12. Protocol Flow 1.3.13. Ordering Rules 1.3.14. Timing Diagram 1.3.15. CCI-P Guidance
1.3.2. Read and Write to Main Memory x
1.3.2.1. Reading from Main Memory 1.3.2.2. Writing to Main Memory
1.3.8. CCI-P Rx Signals x
1.3.8.1. Rx Header and Rx Data Format
1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) x
1.3.10.1. Mixing Byte Enable and Full Cache Line Accesses
1.3.12. Protocol Flow x
1.3.12.1. Upstream Requests 1.3.12.2. Downstream Requests
1.3.13. Ordering Rules x
1.3.13.1. Memory Requests 1.3.13.2. MMIO Requests
1.3.13.1. Memory Requests x
1.3.13.1.1. Memory Write Fence 1.3.13.1.2. Memory Consistency Explained
1.4. AFU Requirements x
1.4.1. Mandatory AFU CSR Definitions 1.4.2. AFU Discovery Flow 1.4.3. AFU_ID
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

1.3. CCI-P Interface

CCI-P implements to memory address spaces:
  • Main memory
  • Memory Mapped I/O (MMIO)
Table 7.  CCI-P Memory Access Types
Memory Type Description
Main Memory

Main memory is the memory attached to the processor and exposed to the operating system. Requests from the AFU to main memory are called upstream requests. Subsequent to this section, main memory is just referred to as memory.

Memory Mapped I/O

I/O memory is implemented as CCI-P requests from the host to the AFU. MMIO is typically used as AFU control registers. How this memory is implemented and organized is up to the AFU developer. The AFU may choose logic, M20Ks or MLABs.

The CCI-P interface defines a request format to access I/O memory using memory mapped I/O (MMIO) requests. Requests from the processor to I/O memory are called downstream requests.

The AFU's MMIO address space is 256 kB in size.

Figure 6. CCI-P SignalsThis figure shows all CCI-P signals grouped into three Tx channels, two Rx channels and some additional control signals.
Table 8.   CCI-P signals
Signal Type Description
Tx/Rx

The flow direction is from the AFU point of view. Tx flows from AFU to FIU. Rx flows from FIU to AFU.

Channels

Grouping of signals that together completely defines the request or response.


Section Content
Signaling Information
Read and Write to Main Memory
Interrupts
UMsg
MMIO Accesses to I/O Memory
CCI-P Tx Signals
Tx Header Format
CCI-P Rx Signals
Multi-Cache Line Memory Requests
Byte Enable Memory Request ( Intel FPGA PAC D5005)
Additional Control Signals
Protocol Flow
Ordering Rules
Timing Diagram
CCI-P Guidance

Level Two Title