Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

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Date 11/04/2019
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Document Table of Contents
Document Table of Contents x
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual x
1.1. About this Document 1.2. Introduction 1.3. CCI-P Interface 1.4. AFU Requirements 1.5. Intel® FPGA Basic Building Blocks 1.6. Device Feature List 1.7. Document Revision History for Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1.1. About this Document x
1.1.1. Intended Audience 1.1.2. Conventions 1.1.3. Related Documentation 1.1.4. Acronym List for Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual 1.1.5. Acceleration Glossary
1.2. Introduction x
1.2.1. FPGA Interface Manager (FIM) 1.2.2. Intel® FPGA Interface Unit (FIU) 1.2.3. Memory and Cache Hierarchy
1.2.2. Intel® FPGA Interface Unit (FIU) x
1.2.2.1. FIU for Intel® FPGA PAC 1.2.2.2. FIU for Intel Integrated FPGA Platform 1.2.2.3. Comparison of FIU Capabilities
1.3. CCI-P Interface x
1.3.1. Signaling Information 1.3.2. Read and Write to Main Memory 1.3.3. Interrupts 1.3.4. UMsg 1.3.5. MMIO Accesses to I/O Memory 1.3.6. CCI-P Tx Signals 1.3.7. Tx Header Format 1.3.8. CCI-P Rx Signals 1.3.9. Multi-Cache Line Memory Requests 1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) 1.3.11. Additional Control Signals 1.3.12. Protocol Flow 1.3.13. Ordering Rules 1.3.14. Timing Diagram 1.3.15. CCI-P Guidance
1.3.2. Read and Write to Main Memory x
1.3.2.1. Reading from Main Memory 1.3.2.2. Writing to Main Memory
1.3.8. CCI-P Rx Signals x
1.3.8.1. Rx Header and Rx Data Format
1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) x
1.3.10.1. Mixing Byte Enable and Full Cache Line Accesses
1.3.12. Protocol Flow x
1.3.12.1. Upstream Requests 1.3.12.2. Downstream Requests
1.3.13. Ordering Rules x
1.3.13.1. Memory Requests 1.3.13.2. MMIO Requests
1.3.13.1. Memory Requests x
1.3.13.1.1. Memory Write Fence 1.3.13.1.2. Memory Consistency Explained
1.4. AFU Requirements x
1.4.1. Mandatory AFU CSR Definitions 1.4.2. AFU Discovery Flow 1.4.3. AFU_ID
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

1.1.4. Acronym List for Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

Table 3.  AcronymsThe "A/B" column indicates whether the term applies to:
  • A: Intel® Xeon® Scalable Platform with Integrated FPGA, referred to as Integrated FPGA Platform throughout this document.
  • B: Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC), referred to as Intel® FPGA PAC throughout this document.
  • A, B: Both packages
Acronyms Expansion A/B Description
AF Accelerator Function A, B Compiled Hardware Accelerator image implemented in FPGA logic that accelerates an application. 
AFU Accelerator Functional Unit A, B Hardware accelerator implemented in FPGA logic which offloads a computational operation for an application from the CPU to improve performance.
BBBs Intel® FPGA Basic Building Blocks A, B

Intel® FPGA Basic Building Blocks are defined as components that can be interfaced with the CCI-P bridge.

For more information, refer to the Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs web page.

CA Caching Agent A

A caching agent (CA) makes read and write requests to the coherent memory in the system. It is also responsible for servicing snoops generated by other Intel® UltraPath Interconnect ( Intel® UPI) agents in the system.

CCI-P Core Cache Interface A, B CCI-P is the standard interface AFUs use to communicate with the host.
CL Cache Line A, B 64-byte cache line
DFL Device Feature Lists A, B DFL defines a structure for grouping like functionality and enumerating them.
FIM FPGA Interface Manager A, B

The FPGA hardware containing the FPGA Interface Unit (FIU) and external interfaces for memory, networking, etc.

The Accelerator Function (AF) interfaces with the FIM at run time.

FIU FPGA Interface Unit A, B FIU is a platform interface layer that acts as a bridge between platform interfaces like PCIe, UPI and AFU-side interfaces such as CCI-P.
KiB 1024 bytes A, B

The term KiB is for 1024 bytes and KB for 1000 bytes. When referring to memory, KB is often used and KiB is implied. When referring to clock frequency, kHz is used, and here K is 1000.

Mdata Metadata A, B

This is a user-defined field, which is relayed from Tx header to the Rx header. It may be used to tag requests with transaction ID or channel ID.

RdLine_I Read Line Invalid A, B

Memory Read Request, with FPGA cache hint set to invalid. The line is not cached in the FPGA, but may cause FPGA cache pollution.

Note: The cache tag tracks the request status for all outstanding requests on Intel® Ultra Path Interconnect ( Intel® UPI). Therefore, even though RdLine_I is marked invalid upon completion, it consumes the cache tag temporarily to track the request status over UPI. This action may result in the eviction of a cache line, resulting in cache pollution. The advantage of using RdLine_I is that it is not tracked by CPU directory; thus it prevents snooping from CPU.
Note: Cache functionality only applies to Intel® Xeon® Processor with Integrated FPGA.
RdLine-S Read Line Shared A Memory read request with FPGA cache hint set to shared. An attempt is made to keep it in the FPGA cache in a shared state.
Rx Receive A, B Receive or input from an AFU's perspective
SMBUS System Management Bus A The System Management Bus (SMBUS) interface performs out-of-band temperature monitoring, configuration during the bootstrap process, and platform debug purposes.
Tx Transmit A, B Transmit or output from an AFU's perspective
Upstream Direction up to CPU A, B Logical direction towards CPU. Example: upstream port means port going to CPU.
UMsg Unordered Message from CPU to AFU A An unordered notification with a 64-byte payload
UMsgH Unordered Message Hint from CPU to AFU A This message is a hint to a subsequent UMsg. No data payload.
Intel® UPI Intel® Ultra Path Interconnect A Intel® 's proprietary coherent interconnect protocol between Intel® cores or other IP.
WrLine_I Write Line Invalid A, B

Memory Write Request, with FPGA cache hint set to Invalid. The FIU writes the data with no intention of keeping the data in FPGA cache.

WrLine_M Write Line Modified A

Memory Write Request, with the FPGA cache hint set to Modified. The FIU writes the data and leaves it in the FPGA cache in a modified state.

WrPush_I Write Push Invalid A

Memory Write Request, with the FPGA cache hint set to Invalid. The FIU writes the data into the processor’s Last Level Cache (LLC) with no intention of keeping the data in the FPGA cache. The LLC it writes to is always the LLC associated with the processor where the DRAM address is homed.

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