Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

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Date 11/04/2019
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Document Table of Contents x
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual x
1.1. About this Document 1.2. Introduction 1.3. CCI-P Interface 1.4. AFU Requirements 1.5. Intel® FPGA Basic Building Blocks 1.6. Device Feature List 1.7. Document Revision History for Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1.1. About this Document x
1.1.1. Intended Audience 1.1.2. Conventions 1.1.3. Related Documentation 1.1.4. Acronym List for Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual 1.1.5. Acceleration Glossary
1.2. Introduction x
1.2.1. FPGA Interface Manager (FIM) 1.2.2. Intel® FPGA Interface Unit (FIU) 1.2.3. Memory and Cache Hierarchy
1.2.2. Intel® FPGA Interface Unit (FIU) x
1.2.2.1. FIU for Intel® FPGA PAC 1.2.2.2. FIU for Intel Integrated FPGA Platform 1.2.2.3. Comparison of FIU Capabilities
1.3. CCI-P Interface x
1.3.1. Signaling Information 1.3.2. Read and Write to Main Memory 1.3.3. Interrupts 1.3.4. UMsg 1.3.5. MMIO Accesses to I/O Memory 1.3.6. CCI-P Tx Signals 1.3.7. Tx Header Format 1.3.8. CCI-P Rx Signals 1.3.9. Multi-Cache Line Memory Requests 1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) 1.3.11. Additional Control Signals 1.3.12. Protocol Flow 1.3.13. Ordering Rules 1.3.14. Timing Diagram 1.3.15. CCI-P Guidance
1.3.2. Read and Write to Main Memory x
1.3.2.1. Reading from Main Memory 1.3.2.2. Writing to Main Memory
1.3.8. CCI-P Rx Signals x
1.3.8.1. Rx Header and Rx Data Format
1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) x
1.3.10.1. Mixing Byte Enable and Full Cache Line Accesses
1.3.12. Protocol Flow x
1.3.12.1. Upstream Requests 1.3.12.2. Downstream Requests
1.3.13. Ordering Rules x
1.3.13.1. Memory Requests Intra-VC Write Observability Inter-VC Write Observability 1.3.13.2. MMIO Requests
1.3.13.1. Memory Requests x
Intra-VC Write Observability Inter-VC Write Observability 1.3.13.1.1. Memory Write Fence 1.3.13.1.2. Memory Consistency Explained
1.4. AFU Requirements x
1.4.1. Mandatory AFU CSR Definitions 1.4.2. AFU Discovery Flow 1.4.3. AFU_ID
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

1.3.13.1. Memory Requests

The CCI-P memory consistency model is different from the PCIe consistency model. The CCI-P implements a “relaxed” memory consistency model.

It relaxes ordering requirements for requests to:
  • Same address
  • Different addresses

Table 33 defines the ordering relationship between two memory requests on CCI-P. The same rules apply for requests to the same address or different addresses. The table entries are defined as follows:

  • Yes: Requests from first column may pass request from first row.
  • No: Requests from first column cannot pass request from first row.
Table 33.  Ordering Rules for Upstream Requests from AFU
Row Bypass Column? Read Write WrFence Interrupt
Read Yes Yes Yes Yes
Write Yes Yes No Yes
WrFence Yes No No No
Interrupt Yes Yes No Yes

You can interpret the table:

  • All operations, except reads, are ordered with regards to WrFences.
  • All other operations are unordered.

Intra-VC Write Observability

Upon receiving a memory write response, the write has reached a local observability point.

Note: VA is not a physical channel and there are no such guarantees for requests to VA.
  • All future reads from AFU to the same physical channel receive the new data.
  • All future writes on the same physical channel replace the data.

Inter-VC Write Observability

A memory write response does NOT mean the data are globally observable across channels. A subsequent read on a different channel may return old data and a subsequent write on a different channel may retire ahead of the original write. WrFence to VA invokes a protocol that is guaranteed to synchronize across VCs. A WrFence VA performs a broadcast operation across all channels.

  • All writes preceding a write fence are pushed to a global observability point.
  • Upon receiving a WrFence response, all future reads from an AFU receive the latest copy of data written, previously, to the write fence being issued.

Section Content
Memory Write Fence
Memory Consistency Explained

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