Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

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Date 11/04/2019
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Document Table of Contents
Document Table of Contents x
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual x
1.1. About this Document 1.2. Introduction 1.3. CCI-P Interface 1.4. AFU Requirements 1.5. Intel® FPGA Basic Building Blocks 1.6. Device Feature List 1.7. Document Revision History for Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1.1. About this Document x
1.1.1. Intended Audience 1.1.2. Conventions 1.1.3. Related Documentation 1.1.4. Acronym List for Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual 1.1.5. Acceleration Glossary
1.2. Introduction x
1.2.1. FPGA Interface Manager (FIM) 1.2.2. Intel® FPGA Interface Unit (FIU) 1.2.3. Memory and Cache Hierarchy
1.2.2. Intel® FPGA Interface Unit (FIU) x
1.2.2.1. FIU for Intel® FPGA PAC 1.2.2.2. FIU for Intel Integrated FPGA Platform 1.2.2.3. Comparison of FIU Capabilities
1.3. CCI-P Interface x
1.3.1. Signaling Information 1.3.2. Read and Write to Main Memory 1.3.3. Interrupts 1.3.4. UMsg 1.3.5. MMIO Accesses to I/O Memory 1.3.6. CCI-P Tx Signals 1.3.7. Tx Header Format 1.3.8. CCI-P Rx Signals 1.3.9. Multi-Cache Line Memory Requests 1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) 1.3.11. Additional Control Signals 1.3.12. Protocol Flow 1.3.13. Ordering Rules 1.3.14. Timing Diagram 1.3.15. CCI-P Guidance
1.3.2. Read and Write to Main Memory x
1.3.2.1. Reading from Main Memory 1.3.2.2. Writing to Main Memory
1.3.8. CCI-P Rx Signals x
1.3.8.1. Rx Header and Rx Data Format
1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) x
1.3.10.1. Mixing Byte Enable and Full Cache Line Accesses
1.3.12. Protocol Flow x
1.3.12.1. Upstream Requests 1.3.12.2. Downstream Requests
1.3.13. Ordering Rules x
1.3.13.1. Memory Requests 1.3.13.2. MMIO Requests
1.3.13.1. Memory Requests x
1.3.13.1.1. Memory Write Fence 1.3.13.1.2. Memory Consistency Explained
1.4. AFU Requirements x
1.4.1. Mandatory AFU CSR Definitions 1.4.2. AFU Discovery Flow 1.4.3. AFU_ID
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

1.2.1. FPGA Interface Manager (FIM)

Figure 1. Overview of FPGA Blocks
The Intel FPGA Accelerator package consists of an FIM and an AFU. The FIM consists of the following:
  • FIU
  • EMIF for interfacing to external memory
  • HSSI for external transceiver interfacing

For more information, refer to your platform for specific details about the FIM implementation.

The FIU acts like a bridge between the AFU and the platform. Figure 1 shows the FIU connection between the PCIe, SMBus for manageability, and the full UPI stack to the host. In addition, the FIM also owns all hard IPs on FPGA (for example PLLs), partial reconfiguration (PR) engine, JTAG atom, IOs, and temperature sensors. The FIM is configured first at boot up and persists until the platform power cycles, whereas the AFU can be dynamically reconfigured. Intel partial reconfiguration technology enables the dynamic reconfiguration capability, where the AFU is defined as a partial reconfiguration region and the FIM is defined as a static region. The interfaces between AFU and FIU provides hot plug capability to pause the traffic, and to re-enumerate the AFU after partial reconfiguration.

The FIM may present one or more interfaces to the AFU, depending on the platform capabilities. This document focuses on CCI-P, an interface for the AFU to communicate with the Intel® Xeon® processor. The CCI-P provides address space isolation and protection using Intel Virtual Technology for Directed I/O (Intel VT-d). The CCI-P has the same protections that are defined for a PCIe function. An AFU is a single function device from a PCIe enumeration and VT-d point of view.

The FIU may also implement manageability functions like error monitoring and reporting, power and temperature monitoring, configuration bootstrap, bitstream security flows, and remote debug to ease the deployment and management of FPGAs in a data center environment. In some implementations, FIU may also have an out-of-band communication interface to the board management controller (BMC).
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