Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

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Date 11/04/2019
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Document Table of Contents
Document Table of Contents x
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual x
1.1. About this Document 1.2. Introduction 1.3. CCI-P Interface 1.4. AFU Requirements 1.5. Intel® FPGA Basic Building Blocks 1.6. Device Feature List 1.7. Document Revision History for Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1.1. About this Document x
1.1.1. Intended Audience 1.1.2. Conventions 1.1.3. Related Documentation 1.1.4. Acronym List for Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual 1.1.5. Acceleration Glossary
1.2. Introduction x
1.2.1. FPGA Interface Manager (FIM) 1.2.2. Intel® FPGA Interface Unit (FIU) 1.2.3. Memory and Cache Hierarchy
1.2.2. Intel® FPGA Interface Unit (FIU) x
1.2.2.1. FIU for Intel® FPGA PAC 1.2.2.2. FIU for Intel Integrated FPGA Platform 1.2.2.3. Comparison of FIU Capabilities
1.3. CCI-P Interface x
1.3.1. Signaling Information 1.3.2. Read and Write to Main Memory 1.3.3. Interrupts 1.3.4. UMsg 1.3.5. MMIO Accesses to I/O Memory 1.3.6. CCI-P Tx Signals 1.3.7. Tx Header Format 1.3.8. CCI-P Rx Signals 1.3.9. Multi-Cache Line Memory Requests 1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) 1.3.11. Additional Control Signals 1.3.12. Protocol Flow 1.3.13. Ordering Rules 1.3.14. Timing Diagram 1.3.15. CCI-P Guidance
1.3.2. Read and Write to Main Memory x
1.3.2.1. Reading from Main Memory 1.3.2.2. Writing to Main Memory
1.3.8. CCI-P Rx Signals x
1.3.8.1. Rx Header and Rx Data Format
1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) x
1.3.10.1. Mixing Byte Enable and Full Cache Line Accesses
1.3.12. Protocol Flow x
1.3.12.1. Upstream Requests 1.3.12.2. Downstream Requests
1.3.13. Ordering Rules x
1.3.13.1. Memory Requests 1.3.13.2. MMIO Requests
1.3.13.1. Memory Requests x
1.3.13.1.1. Memory Write Fence 1.3.13.1.2. Memory Consistency Explained
1.4. AFU Requirements x
1.4.1. Mandatory AFU CSR Definitions 1.4.2. AFU Discovery Flow 1.4.3. AFU_ID
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

1.3.11. Additional Control Signals

Unless otherwise mentioned, all signals are active high.

Table 29.  Clock and Reset
Signal Width (bits) Direction Description
pck_cp2af_softReset 1 Input

Synchronous ACTIVE HIGH soft reset.

When set to 1, AFU must reset all logic. The minimum reset pulse width is 256 pClk cycles. All outstanding CCI-P requests are flushed before de-asserting soft reset.

A soft reset does not reset the FIU.

pClk 1 Input

Primary interface clock. All CCI-P interface signals are synchronous to this clock.

pClkDiv2 1 Input Synchronous and in phase with pClk. 0.5x, the pClk clock frequency.
pClkDiv4 1 Input Synchronous and in phase with pClk. 0.25x, the pClk clock frequency.
uClk_usr 1 Input

The user-defined clock is not synchronous with the pClk.

AFU must synchronize the signals to pClk domain before driving the CCI-P interface.

The AFU load utility programs the user-defined clock frequency before de-asserting pck_cp2af_softReset.

uClk_usrDiv2 1 Input Synchronous with uClk_usr and 0.5x the frequency.
Note: You can set the frequency to a value that is not synchronous with the uClk_usr.
pck_cp2af_pwrState 2 Input

Indicates the current AFU power state request. In response to this, the AFU must attempt to reduce its power consumption. If sufficient power reduction is not achieved, the AFU may be Reset.

2’h0 – AP0 - Normal operation mode

2’h1 – AP1 - Request for 50% power reduction

2’h2 – Reserved

2’h3 – AP2 - Request for 90% power reduction

When pck_cp2af_pwrState is set to AP1, the FIU starts throttling the memory request path to achieve 50% throughput reduction. The AFU is also expected to reduce its power utilization to 50%, by throttling back accesses to FPGA internal memory resources and its compute engines. Similarly upon transition to AP2, the FIU throttles the memory request paths to achieve 90% throughput reduction over normal state, and AFU in turn is expected to reduce its power utilization to 90%.

pck_cp2af_error 1 Input

CCI-P protocol error has been detected and logged in the PORT Error register. This register is visible to the AFU.

It can be used as a signal tap trigger condition.

When such an error is detected, the CCI-P interface stops accepting new requests and sets AlmFull to 1.

In the event of a CCI-P protocol error, you should not expect any outstanding transactions to complete even though the AFU is still active (not held in reset).

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