Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

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Date 11/04/2019
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Document Table of Contents
Document Table of Contents x
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual x
1.1. About this Document 1.2. Introduction 1.3. CCI-P Interface 1.4. AFU Requirements 1.5. Intel® FPGA Basic Building Blocks 1.6. Device Feature List 1.7. Document Revision History for Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1.1. About this Document x
1.1.1. Intended Audience 1.1.2. Conventions 1.1.3. Related Documentation 1.1.4. Acronym List for Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual 1.1.5. Acceleration Glossary
1.2. Introduction x
1.2.1. FPGA Interface Manager (FIM) 1.2.2. Intel® FPGA Interface Unit (FIU) 1.2.3. Memory and Cache Hierarchy
1.2.2. Intel® FPGA Interface Unit (FIU) x
1.2.2.1. FIU for Intel® FPGA PAC 1.2.2.2. FIU for Intel Integrated FPGA Platform 1.2.2.3. Comparison of FIU Capabilities
1.3. CCI-P Interface x
1.3.1. Signaling Information 1.3.2. Read and Write to Main Memory 1.3.3. Interrupts 1.3.4. UMsg 1.3.5. MMIO Accesses to I/O Memory MMIO Reads MMIO Writes Implementation Note for all MMIO Accesses 1.3.6. CCI-P Tx Signals 1.3.7. Tx Header Format 1.3.8. CCI-P Rx Signals 1.3.9. Multi-Cache Line Memory Requests 1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) 1.3.11. Additional Control Signals 1.3.12. Protocol Flow 1.3.13. Ordering Rules 1.3.14. Timing Diagram 1.3.15. CCI-P Guidance
1.3.2. Read and Write to Main Memory x
1.3.2.1. Reading from Main Memory 1.3.2.2. Writing to Main Memory
1.3.8. CCI-P Rx Signals x
1.3.8.1. Rx Header and Rx Data Format
1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) x
1.3.10.1. Mixing Byte Enable and Full Cache Line Accesses
1.3.12. Protocol Flow x
1.3.12.1. Upstream Requests 1.3.12.2. Downstream Requests
1.3.13. Ordering Rules x
1.3.13.1. Memory Requests 1.3.13.2. MMIO Requests
1.3.13.1. Memory Requests x
1.3.13.1.1. Memory Write Fence 1.3.13.1.2. Memory Consistency Explained
1.4. AFU Requirements x
1.4.1. Mandatory AFU CSR Definitions 1.4.2. AFU Discovery Flow 1.4.3. AFU_ID
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

1.3.5. MMIO Accesses to I/O Memory

The CCI-P defines MMIO read and write requests for accessing the AFU register file. MMIO requests are routed from the CPU to the AFU over a single PCIe channel.

MMIO Reads

The AFU receives an MMIO read request over pck_cp2af_sRx.c0. The CCI-P asserts mmioRdValid and drives the MMIO read request on hdr. The c0_ReqMmioHdr structure provides a convenient mapping from a flat bit-vector to MMIO request fields – {address, length, tid}.

The AFU drives an MMIO read response over pck_af2cp_sTx.c2. The AFU asserts mmioRdValid and drives the response header and data on hdr and data, respectively. The AFU is expected to return the request tid with the corresponding response it used to associate the response with request.

The following list describes key attributes of a CCI-P MMIO read request:
  • Data lengths supported are 4 bytes and 8 bytes
  • Response length must match the request length. For example, it is illegal to return two 4-byte responses to an 8-byte MMIO read request
  • Maximum number of outstanding MMIO read requests is limited to 64
  • MMIO reads to undefined AFU registers should still return a response

MMIO Writes

The AFU receives an MMIO write request over pck_cp2af_sRx.c0. The CCI-P asserts mmioWrValid and drives the MMIO write request header and data on hdr and data, respectively. The c0_ReqMmioHdr structure provides a convenient mapping from a flat bit-vector to MMIO request fields – {address, length, tid}. The MMIO write request is posted and no response is expected from the AFU.

The data lengths supported are 4 bytes, 8 bytes, and 64 bytes.

Note: Not supported on all Intel® Xeon® platforms.

Implementation Note for all MMIO Accesses

The following is a list of important considerations when designing an AFU MMIO register file:
  • It is mandatory for the AFU to support 8-byte accesses in order to implement the DFH.
  • Support for 4-byte MMIO accesses is optional. The AFU developer can coordinate with the software application developer to avoid 4-byte accesses.
  • The AFU can accept MMIO requests as they arrive, consecutively, without any delays.
  • Unaligned MMIO accesses results in an error. The software application developer must ensure that the MMIO address is aligned to the request length. For example: 8-byte MMIO request byte address should be a multiple of 8, which means byte address[2:0] should be 0.
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