Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

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Date 11/04/2019
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Document Table of Contents
Document Table of Contents x
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual x
1.1. About this Document 1.2. Introduction 1.3. CCI-P Interface 1.4. AFU Requirements 1.5. Intel® FPGA Basic Building Blocks 1.6. Device Feature List 1.7. Document Revision History for Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1.1. About this Document x
1.1.1. Intended Audience 1.1.2. Conventions 1.1.3. Related Documentation 1.1.4. Acronym List for Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual 1.1.5. Acceleration Glossary
1.2. Introduction x
1.2.1. FPGA Interface Manager (FIM) 1.2.2. Intel® FPGA Interface Unit (FIU) 1.2.3. Memory and Cache Hierarchy
1.2.2. Intel® FPGA Interface Unit (FIU) x
1.2.2.1. FIU for Intel® FPGA PAC 1.2.2.2. FIU for Intel Integrated FPGA Platform 1.2.2.3. Comparison of FIU Capabilities
1.3. CCI-P Interface x
1.3.1. Signaling Information 1.3.2. Read and Write to Main Memory 1.3.3. Interrupts 1.3.4. UMsg 1.3.5. MMIO Accesses to I/O Memory 1.3.6. CCI-P Tx Signals 1.3.7. Tx Header Format 1.3.8. CCI-P Rx Signals 1.3.9. Multi-Cache Line Memory Requests 1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) 1.3.11. Additional Control Signals 1.3.12. Protocol Flow 1.3.13. Ordering Rules 1.3.14. Timing Diagram 1.3.15. CCI-P Guidance
1.3.2. Read and Write to Main Memory x
1.3.2.1. Reading from Main Memory 1.3.2.2. Writing to Main Memory
1.3.8. CCI-P Rx Signals x
1.3.8.1. Rx Header and Rx Data Format
1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) x
1.3.10.1. Mixing Byte Enable and Full Cache Line Accesses
1.3.12. Protocol Flow x
1.3.12.1. Upstream Requests 1.3.12.2. Downstream Requests
1.3.13. Ordering Rules x
1.3.13.1. Memory Requests 1.3.13.2. MMIO Requests
1.3.13.1. Memory Requests x
1.3.13.1.1. Memory Write Fence 1.3.13.1.2. Memory Consistency Explained
1.4. AFU Requirements x
1.4.1. Mandatory AFU CSR Definitions 1.4.2. AFU Discovery Flow 1.4.3. AFU_ID
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

1.3.10.1. Mixing Byte Enable and Full Cache Line Accesses

In some applications, it is necessary for an AFU to access buffers that either start unaligned to 64-byte boundaries or end before the next 64-byte boundary in host memory. An AFU can use a mix of byte enable transactions and full cache line accesses to perform buffer writes that start or end on any boundary. For such a transfer the AFU must not mix byte enable bursts (mode=eMOD_BYTE) with full cache line bursts (mode=eMOD_CL).

In the following example, the AFU writes 152 bytes of an incrementing pattern starting at byte address 0x62EC. Since the first and last byte address being accessed do not line up to 64-byte boundaries, the transfer is broken up into three sections with the start and end sections utilizing byte enables to update a subset of bytes within a 64-byte aligned region of memory. The first section writes 20 bytes to memory, then 128 bytes are written using a full cache line burst, followed by a final write of 4 bytes.
Figure 16. Memory Accessed and Corresponding CCIP Address

Since the first access does not start on a 64-byte boundary, the mode is set to eMOD_BYTE. The byte_start field is 0x2C, the byte_len field is 0x14, and the CCIP address bits 41:2 set to 0x62 and CCIP address bits 1:0 set to 0x3.

Since the second access is aligned to a 2CL boundary the next 128 bytes can be posted as a two beat burst with mode set to eMOD_CL. This access cannot be combined with beats that set mode to eMOD_BYTE because the two modes cannot be interleaved in the same burst.

The third access starts on a 64-byte boundary but only accesses four bytes of memory so the mode is set to eMOD_BYTE. The byte_start field is 0x0, the byte_len field is 0x4, and the CCIP address bits 41:2 set to 0x63 and bits 1:0 set to 0x2.
Figure 17. Mixed Byte Enable and Full Cache Line Access Timing Diagram
Figure 18. Host Memory
Level Two Title