Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

Download PDF
ID 683193
Date 11/04/2019
Public
Document Table of Contents
Document Table of Contents x
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual x
1.1. About this Document 1.2. Introduction 1.3. CCI-P Interface 1.4. AFU Requirements 1.5. Intel® FPGA Basic Building Blocks 1.6. Device Feature List 1.7. Document Revision History for Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1.1. About this Document x
1.1.1. Intended Audience 1.1.2. Conventions 1.1.3. Related Documentation 1.1.4. Acronym List for Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual 1.1.5. Acceleration Glossary
1.2. Introduction x
1.2.1. FPGA Interface Manager (FIM) 1.2.2. Intel® FPGA Interface Unit (FIU) 1.2.3. Memory and Cache Hierarchy
1.2.2. Intel® FPGA Interface Unit (FIU) x
1.2.2.1. FIU for Intel® FPGA PAC 1.2.2.2. FIU for Intel Integrated FPGA Platform 1.2.2.3. Comparison of FIU Capabilities
1.3. CCI-P Interface x
1.3.1. Signaling Information 1.3.2. Read and Write to Main Memory 1.3.3. Interrupts 1.3.4. UMsg 1.3.5. MMIO Accesses to I/O Memory 1.3.6. CCI-P Tx Signals 1.3.7. Tx Header Format 1.3.8. CCI-P Rx Signals 1.3.9. Multi-Cache Line Memory Requests 1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) 1.3.11. Additional Control Signals 1.3.12. Protocol Flow 1.3.13. Ordering Rules 1.3.14. Timing Diagram 1.3.15. CCI-P Guidance
1.3.2. Read and Write to Main Memory x
1.3.2.1. Reading from Main Memory 1.3.2.2. Writing to Main Memory
1.3.8. CCI-P Rx Signals x
1.3.8.1. Rx Header and Rx Data Format
1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) x
1.3.10.1. Mixing Byte Enable and Full Cache Line Accesses
1.3.12. Protocol Flow x
1.3.12.1. Upstream Requests 1.3.12.2. Downstream Requests
1.3.13. Ordering Rules x
1.3.13.1. Memory Requests 1.3.13.2. MMIO Requests
1.3.13.1. Memory Requests x
1.3.13.1.1. Memory Write Fence 1.3.13.1.2. Memory Consistency Explained
1.4. AFU Requirements x
1.4.1. Mandatory AFU CSR Definitions 1.4.2. AFU Discovery Flow 1.4.3. AFU_ID
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

1.2.2.2. FIU for Intel Integrated FPGA Platform

Figure 3.  FIU for Intel Integrated FPGA Platform Block Diagram

The Integrated FPGA Platform has three links connecting the FPGA to the processor: one Intel UPI coherent link and two PCIe Gen3x8 links. It is the function of the FIU to map these three links to the CCI-P interface, such that the AFU sees a single logical communication interface to the host processor with bandwidth equal to the aggregate bandwidth across the three links. Figure 1 shows only the FIU logic associated with mapping UPI and PCIe links to CCI-P.

FIU implements the following functionality for providing the CCI-P mapping:
  • Single logical upstream link: CCI-P maps the three physical links to four virtual channels. PCIe0 to VH0, PCIe1 to VH1, UPI to VL0 and all physical links to VA. An AFU using VA is agnostic of the physical links and it interfaces with a single logical link that can utilize the total upstream bandwidth available to the FPGA. VA implements a weighted de-multiplexer to route the requests to all of the physical links. To design a platform agnostic AFU, the VA virtual channel is the preferred choice.
  • Single point of control: FIU registers a single control interface with the system software stack. All driver interactions to the FIU are directed to PCIe-0. The AFU is discovered and enumerated over PCIe-0.
  • Single identity for VT-d provides a unified address space: All upstream requests use a single function number for address translation. For this reason, the Intel® Xeon® Scalable Platform with Integrated FPGA disables the IOMMU at PCIe-0 and PCIe-1 root ports and instead instantiates an IOMMU in FIU. This IOMMU is used for translating requests going upstream through all three physical links.

Similar to Intel® FPGA PAC, the Integrated FPGA Platform also implements a full set of services provided by the FME and CCI-P ports to deploy and manage the FPGA.

Level Two Title