Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

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Date 11/04/2019
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Document Table of Contents x
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual x
1.1. About this Document 1.2. Introduction 1.3. CCI-P Interface 1.4. AFU Requirements 1.5. Intel® FPGA Basic Building Blocks 1.6. Device Feature List 1.7. Document Revision History for Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1.1. About this Document x
1.1.1. Intended Audience 1.1.2. Conventions 1.1.3. Related Documentation 1.1.4. Acronym List for Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual 1.1.5. Acceleration Glossary
1.2. Introduction x
1.2.1. FPGA Interface Manager (FIM) 1.2.2. Intel® FPGA Interface Unit (FIU) 1.2.3. Memory and Cache Hierarchy
1.2.2. Intel® FPGA Interface Unit (FIU) x
1.2.2.1. FIU for Intel® FPGA PAC 1.2.2.2. FIU for Intel Integrated FPGA Platform 1.2.2.3. Comparison of FIU Capabilities
1.3. CCI-P Interface x
1.3.1. Signaling Information 1.3.2. Read and Write to Main Memory 1.3.3. Interrupts 1.3.4. UMsg 1.3.5. MMIO Accesses to I/O Memory 1.3.6. CCI-P Tx Signals 1.3.7. Tx Header Format 1.3.8. CCI-P Rx Signals 1.3.9. Multi-Cache Line Memory Requests 1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) 1.3.11. Additional Control Signals 1.3.12. Protocol Flow 1.3.13. Ordering Rules 1.3.14. Timing Diagram 1.3.15. CCI-P Guidance
1.3.2. Read and Write to Main Memory x
1.3.2.1. Reading from Main Memory 1.3.2.2. Writing to Main Memory
1.3.8. CCI-P Rx Signals x
1.3.8.1. Rx Header and Rx Data Format
1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) x
1.3.10.1. Mixing Byte Enable and Full Cache Line Accesses
1.3.12. Protocol Flow x
1.3.12.1. Upstream Requests 1.3.12.2. Downstream Requests
1.3.13. Ordering Rules x
1.3.13.1. Memory Requests 1.3.13.2. MMIO Requests
1.3.13.1. Memory Requests x
1.3.13.1.1. Memory Write Fence 1.3.13.1.2. Memory Consistency Explained
1.4. AFU Requirements x
1.4.1. Mandatory AFU CSR Definitions 1.4.2. AFU Discovery Flow 1.4.3. AFU_ID
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

1.4.1. Mandatory AFU CSR Definitions

The following requirements are defined for software access to AFU CSRs.

  1. Software is expected to access 64-bit CSRs as aligned quad words (8 bytes). To modify a field (for example, bit or byte) in a 64-bit register, the entire quad word is read, the appropriate field(s) are modified, and the entire quad word is written back (read-modify-write operation).
  2. Similarly for an AFU supporting 32-bit CSRs, software is expected to access them as aligned double words (4 bytes).

Each CCI-P-compliant AFU is required to implement the four (not including DEV_FEATURE_HDR (DFH) at 0x0000) mandatory registers defined in the table below. If you do not implement these registers or if you implement them incorrectly, AFU discovery could fail or some other unexpected behavior may occur.

Table 41.  Register Attribute Definition
Attribute Expansion Description
RO Read Only The bit is set by hardware only. Software can only read this bit. Writes do not have any effect.
Rsvd Reserved Reserved for future definition. AFU must set them to 0s. Software must ignore these fields.
Table 42 shows both byte and DWORD offsets for the mandatory AFU CSRs. The base address is set by the platform and need not be specified by the AFU.
Table 42.  Mandatory AFU CSRs
Name

DWORD Address

Offset

(CCI-P)

Byte Address

Offset

(Software)

DEV_FEATURE_HDR (DFH)

For bit descriptions, refer to Table 43.
Note: AFU CSRs are 64 bits.
0x0000 0x0000

AFU_ID_L

Lower 64 bits of the AFU_ID GUID.

0x0002 0x0008

AFU_ID_H

Upper 64 bits of the AFU_ID GUID.

0x0004 0x0010
DFH_RSVD0 0x0006 0x0018
DFH_RSVD1 0x0008 0x0020
Figure 23 shows how the AFU might set the mandatory AFU CSRs. You must define your own AFU ID. Note that the AFU uses DWORD addresses. Figure 24 shows how software program might read the AFU ID.
Figure 23. Set the Mandatory AFU Registers in the AFU

The software and the AFU RTL must reference the same AFU ID.

Figure 24. Software Reads the AFU ID
Table 43.  Feature Header CSR DefinitionAddress Offset = 0x0
Bit Attribute Default Description
63:60 RO 0x1 Type: AFU
59:52 Rsvd 0x0 Reserved
51:48 RO 0x0

AFU Minor version number

User defined value
47:41 Rsvd 0x0 Reserved
40 RO N/A

End of List

1’b0: There is another feature header beyond this (see “Next DFH Byte Offset”)

1’b1: This is the last feature header for this AFU

39:16 RO 0x0

Byte offset to the Next Device Feature Header; that is, offset from the current address.

For an example of DFH byte offset, refer to Table 45.

15:12 RO 0x0

AFU Major version number

User defined value
11:0 RO N/A

CCI-P version number

Use the CCIP_VERSION_NUMBER parameter from ccip_if_pkg.sv

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