Intel Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

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Date 11/04/2019
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Document Table of Contents x
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual x
1.1. About this Document 1.2. Introduction 1.3. CCI-P Interface 1.4. AFU Requirements 1.5. Intel® FPGA Basic Building Blocks 1.6. Device Feature List 1.7. Document Revision History for Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual
1.1. About this Document x
1.1.1. Intended Audience 1.1.2. Conventions 1.1.3. Related Documentation 1.1.4. Acronym List for Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual 1.1.5. Acceleration Glossary
1.2. Introduction x
1.2.1. FPGA Interface Manager (FIM) 1.2.2. Intel® FPGA Interface Unit (FIU) 1.2.3. Memory and Cache Hierarchy
1.2.2. Intel® FPGA Interface Unit (FIU) x
1.2.2.1. FIU for Intel® FPGA PAC 1.2.2.2. FIU for Intel Integrated FPGA Platform 1.2.2.3. Comparison of FIU Capabilities
1.3. CCI-P Interface x
1.3.1. Signaling Information 1.3.2. Read and Write to Main Memory 1.3.3. Interrupts 1.3.4. UMsg 1.3.5. MMIO Accesses to I/O Memory 1.3.6. CCI-P Tx Signals 1.3.7. Tx Header Format 1.3.8. CCI-P Rx Signals 1.3.9. Multi-Cache Line Memory Requests 1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) 1.3.11. Additional Control Signals 1.3.12. Protocol Flow 1.3.13. Ordering Rules 1.3.14. Timing Diagram 1.3.15. CCI-P Guidance
1.3.2. Read and Write to Main Memory x
1.3.2.1. Reading from Main Memory 1.3.2.2. Writing to Main Memory
1.3.8. CCI-P Rx Signals x
1.3.8.1. Rx Header and Rx Data Format
1.3.10. Byte Enable Memory Request ( Intel® FPGA PAC D5005) x
1.3.10.1. Mixing Byte Enable and Full Cache Line Accesses
1.3.12. Protocol Flow x
1.3.12.1. Upstream Requests 1.3.12.2. Downstream Requests
1.3.13. Ordering Rules x
1.3.13.1. Memory Requests 1.3.13.2. MMIO Requests
1.3.13.1. Memory Requests x
1.3.13.1.1. Memory Write Fence 1.3.13.1.2. Memory Consistency Explained
1.4. AFU Requirements x
1.4.1. Mandatory AFU CSR Definitions 1.4.2. AFU Discovery Flow 1.4.3. AFU_ID
1. Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual

1.3.13.2. MMIO Requests

The FIU maps the AFU's MMIO address space to a 64-bit prefetchable PCIe* BAR. The AFU's MMIO mapped registers does not have read side-effects; and writes to these registers are able to tolerate write-merging.

For more information about prefetchable BAR, refer to the PCIe Specification.

MMIO requests targeted to the AFU, are sent to the AFU in the same order they were received from the PCIe* link. Similarly, MMIO read responses are returned to the PCIe* link in the same order that the AFU sends it to the CCI-P interface. In other words, the FIU does not re-order MMIO requests or responses targeted to the AFU.

The IA processor can map the PCIe* BAR as either a UC or WC memory type. Table 39 summarizes the IA’s ordering rules for UC and WC typed BAR.

For more information about uncacheable (UC) and write combining (WC) ordering rules, refer to the Intel Software Developers Manual.

Table 39.  MMIO Ordering Rules
Request Memory Attribute Payload Size Memory Ordering Comments
MMIO Write UC 4 bytes, 8 bytes, or 64 bytes Strongly ordered Common case- software behavior
WC 4 bytes, 8 bytes, or 64 bytes (requires Intel® Advanced Vector Extensions 512 ( Intel® AVX-512)) Weakly ordered Special case
MMIO Read UC 4 bytes or 8 bytes Strongly ordered Common case- software behavior
WC 4 bytes or 8 bytes Weakly ordered Special case- streaming read (MOVNTDQA) can cause wider reads. NOT supported
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