Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

7.1.3.2. Virtual Wire Channel

The Virtual Wire (VW) channel allows you to communicate the state of the GPIO tunneled through eSPI bus as in-band messages. The command phase consists of a command opcode, Virtual Wire count, Virtual Wire index, Virtual Wire data, and CRC.
Figure 23. Virtual Wire Packet
The Virtual Wire count indicates the number of Virtual Wire groups communicated by the packet. It is followed by one or more Virtual Wire groups. Each Virtual Wire group consists of two bytes, namely the Virtual Wire index and the Virtual Wire data. The eSPI agent core supports System Event and Server Platform Specific Virtual Wire index.
Table 24.  System Event Virtual Wire Index
Virtual Wire Index Direction Virtual Wire Data Byte Reset
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2h Host to Agent Valid bit for Bit 3- Bit 0 Reserved SLP_S5_n SLP_S4_n SLP_S3_n rsmrst_n
3h Host to Agent Valid bit for Bit 3- Bit 0 Reserved OOB_RST_WARN PLTRST_n SUS_STAT_n espi_reset_n
4h Agent to Host Valid bit for Bit 3- Bit 0 PME_n WAKE_n Reserved OOB_RST_ACK espi_reset_n
5h Agent to Host Valid bit for Bit 3- Bit 0 SLAVE_BOOT_LOAD_STATUS - - SLAVE_BOOT_LOAD_DONE espi_reset_n
6h Agent to Host Valid bit for Bit 3- Bit 0 HOST_RST_ACK RCIN_n SMI_n SCI_n PLTRST_n VW
7h Host to Agent Valid bit for Bit 3- Bit 0 Reserved NMIOUT_n SMIOUT_n HOST_RST_WARN PLTRST_n VW
Table 25.  Server Platform Specific Virtual Wire Index
Virtual Wire Index Direction Virtual Wire Data Byte Reset
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
40h Agent to Host Valid bit for Bit 3- Bit 0 Reserved Reserved Reserved SUS_ACK_n espi_reset_n
41h Host to Agent Valid bit for Bit 3- Bit 0 SLP_A_n Reserved SUS_PWRDN_ACK SUS_WARN_n espi_reset_n
42h Host to Agent Valid bit for Bit 3- Bit 0 Reserved Reserved SLP_WLAN_n SLP_LAN_n rsmrst_n
43h Host to Agent Valid bit for Bit 3- Bit 0 PCH_TO_EC_3 PCH_TO_EC_2 PCH_TO_EC_1 PCH_TO_EC_0 espi_reset_n
44h Host to Agent Valid bit for Bit 3- Bit 0 PCH_TO_EC_7 PCH_TO_EC_6 PCH_TO_EC_5 PCH_TO_EC_4 espi_reset_n
45h Agent to Host Valid bit for Bit 3- Bit 0 EC_TO_PCH_3 EC_TO_PCH_2 EC_TO_PCH_1 EC_TO_PCH_0 espi_reset_n
46h Agent to Host Valid bit for Bit 3- Bit 0 EC_TO_PCH_7 EC_TO_PCH_6 EC_TO_PCH_5 EC_TO_PCH_4 espi_reset_n
47h Host to Agent Valid bit for Bit 3- Bit 0 Reserved Reserved Reserved HOST_C10 PLTRST_n VW