Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

55.2.6. Receiver Logic

The Lightweight UART receiver consists of a 7-, 8-, or 9-bit receiver-shift register and a corresponding 7-, 8-, or 9-bit width of RXFIFO. The RXFIFO can be implemented either in register with configurable depth or a fixed depth that is able to fully utilize a single memory block.

Avalon® memory-mapped host peripherals read the RXFIFO via the Avalon® memory-mapped agent port. The RXFIFO is loaded from the receiver shift register automatically every time a new character is fully received.

These two registers provide double buffering. The RXFIFO can hold previously received character while the subsequent character from RXD stream is being shifted into the receiver shift register.

A host peripheral can monitor the receiver's status by reading the status register's receive character ready (RRDY), RXFIFO overrun error (ROE), RXFIFO underrun error (RUE), RXFIFO full (RFULL), RXFIFO almost full (RAFULL), break detect (BRK), parity error (PE), and framing error (FE) bits. The remaining RXFIFO depth to assert almost full status can be configurable in GUI. The receiver logic checks for five exceptional conditions, which are framing error, parity error, RXFIFO overrun error, RXFIFO underrun error and break detect, in the received data and sets corresponding status register bits. If the RXFIFO overrun error, RXFIFO underrun error, break detect, parity error, or framing error occurs, the corresponding status bit is set and remains HIGH until it is cleared by writing to the status register.

You can only read the data from RXFIFO when the RRDY bits is HIGH, which indicates that RXFIFO is not empty. You will encounter RXFIFO underrun error if you read the data from RXFIFO when the RRDY bits is LOW. When the underrun error occurs, the additional read transaction when RXFIFO is empty will give a default value, which is 0x000F. When RXFIFO is full, the next received character from RXD stream will not be able to fill in RXFIFO and the data will be missing, causing overrun error. The existing data that is stored in RXFIFO will not be overwritten.

You can monitor the RXFIFO filled level by reading the value of RXFIFO_LVL register. Note that when RXFIFO is full, rxfifo level will roll over to 0. Thus, the value 0 of RXFIFO_LVL could either represent RXFIFO is empty only when the status register's receive character ready (RRDY) bit is LOW, otherwise, it means that RXFIFO is full.

The receiver logic automatically detects the correct number of start, stop, and parity bits in the serial RXD stream as required by the RS-232 specification.