Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

34.4. Interface

The following are top level signals from core

Table 374.  Clock and Reset Signals

Signal

Width

Direction

Description

clk

1

Input

System Clock

rst_n

1

Input

System asynchronous reset. The signal is asserted asynchronously, but is de-asserted synchronously after the rising edge of ssi_clk. The synchronization must be provided external to this component.

Table 375.   Avalon® -MM Agent Interface Signals

Signal

Width

Direction

Description

avs_read

1

Input

Avalon® -MM read control. Asserted to indicate a read transfer. If present, readdata is required.

avs_write

1

Input

Avalon® -MM write control. Asserted to indicate a write transfer. If present, writedata is required.

avs_byteenable dqm_width

Input

Enables specific byte lane(s) during transfer. Each bit corresponds to a byte in avs_writedata and avs_readdata.

avs_address controller_addr_width

Input

Avalon® -MM address bus.

avs_writedata sdram_data_width

Input

Avalon® -MM write data bus. Driven by the bus host (bridge unit) during write cycles.

avs_readdata sdram_data_width

Output

Avalon® -MM readback data. Driven by the altera_spi during read cycles.

avs_readdatavalid

1

Output

Asserted to indicate that the avs_readdata signals contains valid data in response to a previous read request.

avs_waitrequest

1

Output

Asserted when it is unable to respond to a read or write request.

Table 376.  Tristate Conduit Host / SDRAM Interface Signals

Signal

Width

Direction

Description

tcm_grant

1

Input

When asserted, indicates that a tristate conduit host has been granted access to perform transactions. tcm_grant is asserted in response to the tcm_request signal and remains asserted until 1 cycle following the deassertion of request.

Valid only when pin sharing mode is enabled.

tcm_request

1

Output

The meaning of tcm_request depends on the state of the tcm_grant signal, as the following rules dictate:

  • When tcm_request is asserted and tcm_grant is deasserted, tcm_request is requesting access for the current cycle.
  • When tcm_request is asserted and tcm_grant is asserted, tcm_request is requesting access for the next cycle; consequently, tcm_request should be deasserted on the final cycle of an access.

Because tcm_request is deasserted in the last cycle of a bus access, it can be reasserted immediately following the final cycle of a transfer, making both rearbitration and continuous bus access possible if no other hosts are requesting access.

Once asserted, tcm_request must remain asserted until granted; consequently, the shortest bus access is 2 cycles.

Valid only when pin-sharing mode is enabled.

sdram_dq_width sdram_data_width

Output

SDRAM data bus output.

Valid only when pin-sharing mode is enabled

sdram_dq_in sdram_data_width

Input

SDRAM data bus input.

Valid only when pin-sharing mode is enabled.

sdram_dq_oen

1

Output

SDRAM data bus output enable.

Valid only when pin-sharing mode is enabled.

sdram_dq sdram_data_width

Input/Output

SDRAM data bus.

Valid only when pin-sharing mode is disabled.

sdram_addr sdram_addr_width

Output

SDRAM address bus.

sdram_ba sdram_bank_width

Output

SDRAM bank address.

sdram_dqm dqm_width

Output

SDRAM data mask. When asserted, it indicates to the SDRAM chip that the corresponding data signal is suppressed. There is one DQM line per 8 bits data lines

sdram_ras_n

1

Output

Row Address Select. When taken LOW, the value on the tcm_addr_out bus is used to select the bank and activate the required row.

sdram_cas_n

1

Output

Column Address Select. When taken LOW, the value on the tcm_addr_out bus is used to select the bank and required column. A read or write operation will then be conducted from that memory location, depending on the state of tcm_we_out.

sdram_we_n

1

Output

SDRAM Write Enable, determines whether the location addressed by tcm_addr_out is written to or read from.

0=Read

1=Write

sdram_cs_n  

Output

SDRAM Chip Select. When taken LOW, will enables the SDRAM device.

sdram_cke

1

Output

SDRAM Clock Enable. The SDRAM controller does not support clock-disable modes. The SDRAM controller permanently asserts the tcm_sdr_cke_out signal on the SDRAM.

Note: The SDRAM controller does not have any configurable control status registers (CSR).