Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

38.4. Parameters

Generation-time parameters control the features present in the hardware.The table below lists and describes the parameters you can configure.

Table 403.  Parameters for VIC Core
Parameter Legal Values Default Description
Number of interrupts 1 – 32 8 Specifies the number of irq_input interrupt interfaces.
RIL width 1 – 6 4 Specifies the bit width of the requested interrupt level.
Daisy chain enable True / False False Specifies whether or not to include an input interface for daisy chaining VICs together.
Override Default Interrupt Signal Latency True/False False

Allows manual specification of the interrupt signal latency.

Manual Interrupt Signal Latency 2 – 5 2

Specifies the number of cycles it takes to process incoming interrupt signals.

Because multiple VICs can exist in a single system, Platform Designer assigns a unique interrupt controller identification number to each VIC generated.

Keep the following considerations in mind when connecting the core in your Platform Designer system:

  • The CSR access interface (csr_access) connects to a data host port on your processor.
  • The daisy chain input interface (interrupt_controller_in) is only visible when the daisy chain enable option is on.
  • The interrupt controller output interface (interrupt_controller_out) connects either to the EIC port of your processor, or to another VIC’s daisy chain input interface (interrupt_controller_in).
  • For Platform Designer interoperability, the VIC core includes an Avalon® -MM host port. This host interface is not used to access memory or peripherals. Its purpose is to allow peripheral interrupts to connect to the VIC in Platform Designer. The port must be connected to an Avalon® -MM agent to create a valid Platform Designer system. Then at system generation time, the unused host port is removed during optimization. The most simple solution is to connect the host port directly into the CSR access interface (csr_access).
  • Platform Designer automatically connects interrupt sources when instantiating components. When using the provided HAL device driver for the VIC, daisy chaining multiple VICs in a system requires that each interrupt source is connected to exactly one VIC. You need to manually remove any extra connections.