Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

54.2. IP Parameters

Figure 177. Cache Coherency Translator Interface
Table 496.  Parameter List
Parameter Legal Values Description
General
CONTROL_INTERFACE 0:None, 1:GPIO, 2:CSR

Control interface to embed the cacheability and coherency settings to the IP.

Address Width 20:38 Address width for the AXI-4 and ACE-LITE interface.
Data Width 128, 256, 512 Data width for the AXI-4 and ACE-LITE interface.
AXM ID Width 1:18 ID width for ACE-LITE interface. 48 49
AXS ID Width 1:18 ID Width for AXI-4 interface.
Acceptance
Read Issuing Capability 4 bits integer Specifies the maximum number of pending reads that the ACE-LITE manager issues.
Write Issuing Capability 4 bits integer Specifies the maximum number of pending writes that the ACE-LITE manager issues.
Combined Issuing Capability 4 bits integer Specifies the maximum number of pending transactions that the ACE-LITE manager issues.
ACE-LITE Transaction Control for Read Channel
ARDOMAIN_OVERRIDE 2 bits STD_LOGIC Default ACE-LITE Manager ARDOMAIN value for override.
ARBAR_OVERRIDE 2 bits STD_LOGIC Default ACE-LITE Manager ARBAR value for ovveride.
ARSNOOP_OVERRIDE 4 bits STD_LOGIC Default ACE-LITE Manager ARSNOOP value for override.
ARCACHE_OVERRIDE_EN 0,1 Enable/Disable ACE-LITE Manager ARCACHE override. If override is disabled, the axm_m0_arcache = axs_s0_arcache.
ARCACHE_OVERRIDE 4 bits STD_LOGIC Default ACE-LITE Manager ARCACHE value for override.
ACE-LITE Transaction Control for Write Channel Tab
AWDOMAIN_OVERRIDE 2 bits STD_LOGIC Default ACE-LITE Manager AWDOMAIN value for override.
AWBAR_OVERRIDE 2 bits STD_LOGIC Default ACE-LITE Manager AWBAR value for embedded.
AWSNOOP_OVERRIDE 3 bits STD_LOGIC Default ACE-LITE Manager AWSNOOP value for override.
AWCACHE_OVERRIDE_EN 0,1 Enable/Disable ACE-LITE Manager AWCACHE override. If override is disabled, the axm_m0_awcache = axs_s0_awcache.
AWCACHE_OVERRIDE 4 bits STD_LOGIC Default ACE-LITE Manager AWCACHE value for override.
User Selection
AxPROT_OVERRIDE_EN 0,1 Enable/Disable ACE-LITE Manager AWPROT and ARPROT override. If override is disabled, the axm_m0_arprot = axs_s0_arprot and axm_m0_awprot = axs_s0_awprot.
AxPROT_OVERRIDE 3 bits Default ACE-LITE Manager AWPROT & ARPROT value for override.
AxUSER_SELECTION 50 0,1

Default ACE-LITE Manager's AWUSER & ARUSER.

0 - Route to CCU.

1 - Bypass CCU.

48 AXM ID Width must be equal or greater than the AXS ID Width.
49 If AXS ID Width is larger than AXM ID Width, error message is prompted. If AXS ID Width is smaller than AXM ID Width, zero padding is applied to the most significant bit (MSB) of the ID.
50 AxUSER_SELECTION is for Intel Agilex® 7 devices only.