Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

24.3.3. Interface Signals

Table 266.  Interface Signals
Signal Width Direction Description
wrclock 1 Input Clock signal for input interface.
reset_n 1 Input Asynchronous reset signal that is associated with wrclock.
rdclock 1 Input Clock signal for output interface. This signal is only available with the dual mode selection.
rdreset_n 1 Input Asynchronous reset signal that is associated with rdclock. This signal is only available with the dual mode selection.
avalonmm_write_slave_write 1 Input Write control signal. Enable when the input type is AVALONMM_WRITE.
avalonmm_write_slave_writedata 8-256 Input Write data bus. Enable when the input type is AVALONMM_WRITE.
avalonst_sink_channel 8 Input Channel bus. Enable when the input type is AVALONST_SINK.
avalonst_sink_data 32 Input Data bus. Enable when the input type is AVALONST_SINK.
avalonst_sink_empty 1 Input Empty signal. Enable when the input type is AVALONST_SINK.
avalonst_sink_endofpacket 1 Input End of packet signal. Enable when the input type is AVALONST_SINK.
avalonst_sink_error 8 Input Error signal. Enable when the input type is AVALONST_SINK.
avalonst_sink_startofpacket 1 Input Start of packet signal. Enable when the input type is AVALONST_SINK.
avalonst_sink_valid 1 Input Valid signal. Enable when the input type is AVALONST_SINK.
avalonmm_read_slave_read 1 Input Read control signal. Enable when the input type is AVALONMM_READ.
avalonmm_read_slave_readdata 8-256 Output Read data bus. Enable when the input type is AVALONMM_READ.
avalonst_source_channel 8 Output Channel bus. Enable when the input type is AVALONST_SOURCE.
avalonst_source_data 32 Output Data bus. Enable when the input type is AVALONST_SOURCE.
avalonst_source_empty 1 Output Empty signal. Enable when the input type is AVALONST_SOURCE.
avalonst_source_endofpacket 1 Output End of packet signal. Enable when the input type is AVALONST_SOURCE.
avalonst_source_error 8 Output Error signal. Enable when the input type is AVALONST_SOURCE.
avalonst_source_startofpacket 1 Output Start of packet signal. Enable when the input type is AVALONST_SOURCE.
avalonst_source_valid 1 Output Valid signal. Enable when the input type is AVALONST_SOURCE.
wrclk_control_slave_address 3 Input Address bus. Enable when the status interface for input is enabled.
wrclk_control_slave_read 1 Input Read control signal. Enable when the status interface for input is enabled.
wrclk_control_slave_readdata 32 Output Read data bus. Enable when the status interface for input is enabled.
wrclk_control_slave_write 1 Input Write control signal. Enable when the status interface for input is enabled.
wrclk_control_slave_writedata 32 Input Write data bus. Enable when the status interface for input is enabled.
rdclk_control_slave_address 3 Input Address bus. Enable when the status interface for output is enabled.
rdclk_control_slave_read 1 Input Read control signal. Enable when the status interface for output is enabled.
rdclk_control_slave_readdata 32 Output Read data bus. Enable when the status interface for output is enabled.
rdclk_control_slave_write 1 Input Write control signal. Enable when the status interface for output is enabled.
rdclk_control_slave_writedata 32 Input Write data bus. Enable when the status interface for output is enabled.
wrclk_control_slave_irq 1 Output Interrupt signal for input status register. Enable when IRQ and status interface for input are enabled.
rdclk_control_slave_irq 1 Output Interrupt signal for output status register. Enable when IRQ and status interface for output are enabled.