Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

15.4. Interface

Figure 45.  Intel FPGA Avalon® I2C (Host) Core
Table 123.   Intel FPGA Avalon® I2C (Host) Core Signals
Signal Width Direction Description
Clock/Reset
clk 1 Input System clock source, Minimum clock frequency is 10 MHz.
rst_n 1 Input

System asynchronous reset source,

Note: This signal is asynchronously asserted and synchronously de-asserted. The synchronous de-assertion must be provided externally to this peripheral.
Avalon® -MM Agent
addr 4 Input Avalon® -MM address bus.

The address bus is in the unit of word addressing. For example, addr[2:0] = 0x0 is targeting the first word of the cores memory map space and addr[2:0] = 0x1 is targeting the second word.

read 1 Input Avalon® -MM read control
write 1 Input Avalon® -MM write control
readdata 32 Output Avalon® -MM read data bus
writedata 32 Input Avalon® -MM write data bus
Avalon® -ST Source 22
src_data 8 Output I2C data from receive data FIFO (RX_DATA)
src_valid 1 Output Indicates src_data bus is valid
src_ready 1 Input Indication from sink port that it is ready to consume src_data
Avalon® -ST Sink22
snk_data 10 Input 10-bit value driven by source port to transfer command FIFO (TFR_CMD)
snk_valid 1 Input Indication from source port that snk_data is valid
snk_ready 1 Output Indication from sink port that it is ready to consume snk_data
Serial Interface
scl_oe 1 Output

Output enable for open drain buffer that drives SCL pin

1: SCL line pulled low

0: Open drain buffer is tri-stated and SCL line is externally pulled high

sda_oe 1 Output

Output enable for open drain buffer that drives SDA pin

1: SDA line pulled low

0: Open drain buffer is tri-stated and SDA line is externally pulled high

scl_in 1 Input Input path of I2C’s open drain buffer
sda_in 1 Input It is from input path of I2C’s open drain buffer
Interrupt
intr 1 Output Active high level interrupt output to host processor
22 These signals are not used if “Interface for transfer command FIFO and receive data FIFO accesses” is set to Avalon® -MM Agent. This setting can be configured through Platform Designer.