Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

35.2.2. Parameters

Table 377.  Video Sync Generator Parameters
Parameter Name Description
Horizontal Sync Pulse Pixels The width of the h-sync pulse in number of pixels.
Total Vertical Scan Lines The total number of lines in one video frame. The value is the sum of the following parameters: Number of Rows, Vertical Blank Lines, and Vertical Front Porch Lines.
Number of Rows The number of active scan lines in each video frame.
Horizontal Sync Pulse Polarity The polarity of the h-sync pulse; 0 = active low and 1 = active high.
Horizontal Front Porch Pixels The number of blanking pixels that follow the active pixels. During this period, there is no data flow from the Avalon® -ST sink port to the LCD output data port.
Vertical Sync Pulse Polarity The polarity of the v-sync pulse; 0 = active low and 1 = active high.
Vertical Sync Pulse Lines The width of the v-sync pulse in number of lines.
Vertical Front Porch Lines The number of blanking lines that follow the active lines. During this period, there is no data flow from the Avalon® -ST sink port to the LCD output data port.
Number of Columns The number of active pixels in each line.
Horizontal Blank Pixels The number of blanking pixels that precede the active pixels. During this period, there is no data flow from the Avalon® -ST sink port to the LCD output data port.
Total Horizontal Scan Pixels The total number of pixels in one line. The value is the sum of the following parameters: Number of Columns, Horizontal Blank Pixel, and Horizontal Front Porch Pixels.
bits Per Pixel The number of bits required to transfer one pixel. Valid values are 1 and 3. This parameter, when multiplied by Data Stream Bit Width must be equal to the total number of bits in one pixel. This parameter affects the operating clock frequency, as shown in the following equation:


Operating clock frequency = (bits per pixel) * (Pixel_rate), where 
Pixel_rate (in MHz) = ((Total Horizontal Scan Pixels) * (Total Vertical Scan Lines) * (Display refresh rate in Hz))/1000000.

Vertical Blank Lines The number of blanking lines that proceed the active lines. During this period, there is no data flow from the Avalon® -ST sink port to the LCD output data port.
Data Stream Bit Width The width of the inbound and outbound data.