Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

32.6.3. Register Maps

The SG-DMA controller core has three registers accessible from its Avalon® -MM interface; status, control and next_descriptor_pointer. Software can configure the core and determines its current status by accessing the registers.

The control/status register has a 32-bit interface without byte-enable logic, and therefore cannot be properly accessed by a host with narrower data width than itself. To ensure correct operation of the core, always access the register with a host that is at least 32 bits wide.

Table 358.  Register Map
32-bit Word Offset (Byte Offset) Register Name Reset Value Description
base + 0 (0x0) status 0 This register indicates the core’s current status such as what caused the last interrupt and if the core is still processing descriptors. See the status Register Map table for the status register map.
base + 1 (0x4) version 1 Indicate the hardware version number. Only being used by software driver for software backward compatibility purpose.
base + 4 (0x10) control 0 This register specifies the core’s behavior such as what triggers an interrupt and when the core is started and stopped. The host processor can configure the core by setting the register bits accordingly. See the Control Register Bit Map table for the control register map.
base + 8 (0x20) next_descriptor_pointer 0 This register contains the address of the next descriptor to process. Set this register to the address of the first descriptor as part of the system initialization sequence.

Intel recommends that user applications clear the RUN bit in the control register and wait until the BUSY bit of the status register is set to 0 before reading this register.

Table 359.  Control Register Bit Map
Bit Bit Name Access Description
0 IE_ERROR R/W When this bit is set to 1, the core generates an interrupt if an Avalon® -ST error occurs during descriptor processing. (1)
1 IE_EOP_ENCOUNTERED R/W When this bit is set to 1, the core generates an interrupt if an EOP is encountered during descriptor processing. (1)
2 IE_DESCRIPTOR_COMPLETED R/W When this bit is set to 1, the core generates an interrupt after each descriptor is processed. (1)
3 IE_CHAIN_COMPLETED R/W When this bit is set to 1, the core generates an interrupt after the last descriptor in the list is processed, that is when the core encounters a descriptor with a cleared OWNED_BY_HW bit. (1)
4 IE_GLOBAL R/W When this bit is set to 1, the core is enabled to generate interrupts.
5 RUN R/W Set this bit to 1 to start the descriptor processor block which subsequently initiates DMA transactions. Prior to setting this bit to 1, ensure that the register next_descriptor_pointer is updated with the address of the first descriptor to process. The core continues to process descriptors in its queue as long as this bit is 1.

Clear this bit to stop the core from processing the next descriptor in its queue. If this bit is cleared in the middle of processing a descriptor, the core completes the processing before stopping. The host processor can then modify the remaining descriptors and restart the core.

6 STOP_DMA_ER R/W Set this bit to 1 to stop the core when an Avalon® -ST error is encountered during a DMA transaction. This bit applies only to stream-to-memory configurations.
7 IE_MAX_DESC_PROCESSED R/W Set this bit to 1 to generate an interrupt after the number of descriptors specified by MAX_DESC_PROCESSED are processed.
8 .. 15 MAX_DESC_PROCESSED R/W Specifies the number of descriptors to process before the core generates an interrupt.
16 SW_RESET R/W Software can reset the core by writing to this bit twice. Upon the second write, the core is reset. The logic which sequences the software reset process then resets itself automatically.

Executing a software reset when a DMA transfer is active may result in permanent bus lockup until the next system reset. Hence, Intel recommends that you use the software reset as your last resort.

17 PARK R/W Setting this bit to 0 causes the SG-DMA controller core to clear the OWNED_BY_HW bit in the descriptor after each descriptor is processed. If the PARK bit is set to 1, the core does not clear the OWNED_BY_HW bit, thus allowing the same descriptor to be processed repeatedly without software intervention. You also need to set the last descriptor in the list to point to the first one.
18 DESC_POLL_EN R/W Set this bit to 1 to enable polling mode. When you set this bit to 1, the core continues to poll for the next descriptor until the OWNED_BY_HW bit is set. The core also updates the descriptor pointer to point to the current descriptor.
19 Reserved
20..30 TIMEOUT_COUNTER RW Specifies the number of clocks to wait before polling again. The valid range is 1 to 255. The core also updates the next_desc_ptr field so that it points to the next descriptor to read.
31 CLEAR_INTERRUPT R/W Set this bit to 1 to clear pending interrupts.
Note :
  1. All interrupts are generated only after the descriptor is updated.

Intel recommends that you read the status register only after the RUN bit in the control register is cleared.

Table 360.  Status Register Bit Map
Bit Bit Name Access Description
0 ERROR R/C (1) (2) A value of 1 indicates that an Avalon® -ST error was encountered during a transfer.
1 EOP_ENCOUNTERED R/C A value of 1 indicates that the transfer was terminated by an end-of-packet (EOP) signal generated on the Avalon® -ST source interface. This condition is only possible in stream-to-memory configurations.
2 DESCRIPTOR_COMPLETED R/C (1) (2) A value of 1 indicates that a descriptor was processed to completion.
3 CHAIN_COMPLETED R/C (1) (2) A value of 1 indicates that the core has completed processing the descriptor chain.
4 BUSY R (3) A value of 1 indicates that descriptors are being processed.
This bit is set to 1 on the next clock cycle after the RUN bit is asserted and does not get cleared until one of the following event occurs:
  • After the processing of the descriptor completes and the RUN bit is cleared.
  • When an error condition occurs, the STOP_DMA_ER bit is set to 1 and the processing of the current descriptor completes.
5 .. 31 Reserved
Note :
  1. This bit must be cleared after a read is performed. Write one to clear this bit.
  2. This bit is updated by hardware after each DMA transfer completes. It remains set until software writes one to clear.
  3. This bit is continuously updated by the hardware.