Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

41.3. Configuration

The id and timestamp register values are determined at system generation time based on the configuration of the Platform Designer system and the current time. You can add only one system ID core to an Platform Designer system, and its name is always sysid.

After system generation, you can examine the values stored in the id and timestamp registers by opening the IP Parameter Editor for the System ID core.

Since a unique timestamp value is added to the System ID HDL file each time you generate the Platform Designer system, the Intel® Quartus® Prime software recompiles the entire system if you have added the system as a design partition.
Note: In Intel® Quartus® Prime Pro Edition, the Platform Designer generation process needs an additional TCL script for manual execution to have a unique timestamp value.
Follow these steps to have a unique timestamp value using the Intel® Quartus® Prime Pro Edition version:
  1. Create a Platform Designer system with the System ID core.
  2. Go to View>System Scripting. Click on User Scripts and direct to soceds/examples/hardware/<*_ghrd folder>/update_sysid.tcl (you may also copy the script into your local directory and point to it).
  3. Click on Run Script.
  4. After you run the script, the IP Parameter Editor window appears. Ensure that no error message is shown under System Scripting Messages box.
  5. To save changes to your .ip file, select File > Save option.
  6. Select File > Open to open your main QSYS system. Switch toSystem tab of the Open window, navigate and select your main QSYS system file in the Platform designer system field (on the bottom).
    Note: You must change Files of Type field to All Files (*.qsys), then click Open.
  7. Click on Sync System Info in Platform Designer.
  8. Click on Generate HDL.