Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

55.5.4.3. Status Register

The status register consists of individual bits that indicate conditions inside the lightweight UART core. Each status bit is associated with a corresponding interrupt-enable bit in the control register. The status register can be read at any time. Reading does not change the value of any of the bits. Writing zero to the status register clears the DCTS, E, TOE, ROE, BRK, FE, and PE bits.
Table 524.  Status Register Bits
Bit Name Access Description
15 RAFULL Read-only RXFIFO almost full. The remaining RXFIFO depth to assert almost full status can be configurable in GUI.
14 RFULL Read-only RXFIFO full
13 RUE55 Read-write RXFIFO underrun error. This error occurs when you issue a read transaction when RXFIFO is empty. In this state, the default value is 0x0F.
12 EOP55 Read-write End of packet encountered
Note: Only applicable if parameter Include end-of-packet is enabled.
11 CTS Read-only Clear-to-send (CTS) signal
Note: Only applicable if parameter Include CTS/RTS is enabled.
10 DCTS55 Read-write Change in clear to send (CTS) signal
Note: Only applicable if parameter Include CTS/RTS is enabled.
9 Reserved N/A Reserved
8 E Read-only

Exception condition (framing error, parity error, TXFIFO overrun error,

RXFIFO overrun error, RXFIFO underrun error, or break detect) encountered.

7 RRDY Read-only

Receive character ready

0: RXFIFO is empty

1: RXFIFO is not empty

6 TRDY Read-only

Transmit ready

0: TXFIFO is full

1: TXFIFO is not full

5 TMT Read-only

Transmit data empty

Indicates that both TXFIFO and transmit shift register is empty

4 TOE55 Read-write

TXFIFO overrun error

This error occurs when you issue a write transaction when TXFIFO is full. Any write data to TXFIFO at this state causes missing data.

3 ROE55 Read-write

RXFIFO overrun error

This error occurs when RXFIFO is full and that there is newly received character from the receiver shift register. This causes the latest received data to be missing.

2 BRK55 Read-write Break detect
1 FE55 Read-write Framing error
0 PE55 Read-write Parity error
55 sticky bits