Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

39.5.1. Register Maps

This section describes the register maps for the data pattern generator and checker cores.

Data Pattern Generator Control Registers

Table 413.  Data Pattern Generator Register Map
Offset Register Name
base + 0 Enable
base + 1 Pattern Select
base + 2 Inject Error
base + 3 Preamble Control
base + 4 Preamble Character (Lower Bits)
base + 5 Preamble Character (Higher Bits)
Table 414.  Enable Field Descriptions
Bit(s) Name Access Description
[0] EN RW Setting this bit to 1 enables the data pattern generator core.
[31:1] Reserved
Note to Table 29–4 :
  1. When the core is enabled, only the Enable register and the Inject Error register have write access. Write access to all other registers are ignored.The first valid data is observed from the Avalon® -ST Source interface at the fourth cycle after the Enable bit is set. When the core is disabled, the final output is observed at the next clock cycle.
Table 415.  Pattern Select Field Descriptions
Bit(s) Name Access Description
[0] PRBS7 RW Setting this bit to 1 outputs a PRBS 7 pattern with T [7, 6].
[1] PRBS15 RW Setting this bit to 1 outputs a PRBS 15 pattern with T [15, 14].
[2] PRBS23 RW Setting this bit to 1 outputs a PRBS 23 pattern with T [23, 18].
[3] PRBS31 RW Setting this bit to 1 outputs a PRBS 31 pattern with T [31, 28].
[4] HF RW Setting this bit to 1 outputs a constant pattern of 0101010101… bits.
[5] LF RW Setting this bit to 1 outputs a constant word pattern of 1111100000 for 10-bit words, or 11110000 for 8-bit words.
[31:8] Reserved
Note to Table 29–5 :
  1. This register is one-hot encoded where only one of the pattern selector bits should be set to 1. For all other settings, the behaviors are undefined.

This register allows you to set the error inject bit and insert one bit of error into the stream.

Table 416.  Inject Error Field Descriptions   (Note 1)
Bit(s) Name Access Description
[0] IJ RW Setting this bit to 1 injects error into the stream. If the IJ bit is set to 1 when the core is enabled, the bit resets itself to 0 at the next clock cycle when the error is injected.
[31:1] Reserved
Note to Table 29–6 :
  1. The LSB of the data beat is flipped at the fourth clock cycle after the IJ bit is set (if not being backpressured by the sink when it is valid). The data beat that is injected with error might not be observed from the source if the core is disabled within the next two cycles after IJ bit is set to 1.

This register enables preamble and set the number of cycles to output the preamble character.

Table 417.  Preamble Control Field Descriptions
Bit(s) Name Access Description
[0] EP RW Setting this bit to 1, at the start of pattern generation, enables the preamble character to be sent for Numbits cycles before switching over to the selected pattern.
[7:1] Reserved
[15:8] Numbits RW The number of bits to repeat the preamble character.
[31:16] Reserved

This register is for the user-defined preamble character (bit 0-31).

Table 418.  Preamble Character Low Bits Field Descriptions
Bit(s) Name Access Description
[31:0] Preamble Character (Lower Bits) RW Sets bit 31-0 for the preamble character to output.

This register is for the user-defined preamble character (bit 32-39) but is ignored if the ST_DATA_W value is set to 32.

Table 419.  Preamble Character High Bits Field Descriptions
Bit(s) Name Access Description
[7:0] Preamble Character (Higher Bits) RW Sets bit 39-32 for the preamble character. This is ignored when the ST_DATA_W value is set to 32.
[31:8] Reserved

Data Pattern Checker Control and Status Registers

Table 420.  Data Pattern Checker Control and Status Register Map
Offset Register Name
base + 0 Status
base + 1 Pattern Set
base + 2 Counter Control
base + 3 NumBits (Lower Bits)
base + 4 NumBits (Higher Bits)
base + 5 NumErrors (Lower Bits)
base + 6 NumErrors (Higher Bits)
Table 421.  Status Field Descriptions
Bit(s) Name Access Description
[0] EN RW Setting this bit to 1 enables pattern checking.
[1] LK R Indicate lock status (writing to this bit has no effect).
[31:2] Reserved
Note to Table 29–11 :
  1. When the core is enabled, only the Status register’s EN bit and the counter control register have write access. Write access to all other registers are ignored.
Table 422.  Pattern Select Field Descriptions
Bit(s) Name Access Description
[0] PRBS7 RW Setting this bit to 1 compares the data to a PRBS 7 pattern with T [7, 6].
[1] PRBS15 RW Setting this bit to 1 compares the data to a PRBS 15 pattern with T [15, 14].
[2] PRBS23 RW Setting this bit to 1 compares the data to a PRBS 23 pattern with T [23, 18].
[3] PRBS31 RW Setting this bit to 1 compares the data to a PRBS 31 pattern with T [31, 28].
[4] HF RW Setting this bit to 1 compares the data to a constant pattern of 0101010101… bits.
[5] LF RW Setting this bit to 1 compares the data to a constant word pattern of 1111100000 for 10-bit words, or 11110000 for 8-bit words.
[31:8] Reserved
Note to Table 29–12 :
  1. This register is one-hot encoded where only one of the pattern selector bits should be set to 1. For all other settings, the behaviors are undefined.

This register snapshots and resets the NumBits, NumErrors, and also the internal counters.

Table 423.  Counter Control Field Descriptions
Bit(s) Name Access Description
[0] SN W Writing this bit to 1 captures the number of bits received and number of error bits received from the internal counters to the respective NumBits and NumErrors registers within the same clock cycle.

Writing this bit to 1 after disabling the core will still capture the correct values from the internal counters to the NumBits and NumErrors registers.

[1] RST W Writing this bit to 1 resets all internal counters and statistics. This bit resets itself automatically after the reset process. Re-enabling the core does not automatically reset the number of bits received and number of error bits received in the internal counter.
[31:2] Reserved

This register is the lower word of the 64-bit bit counter snapshot value. The register is reset when the component-reset is asserted or when the RST bit is set to 1.

Table 424.  NumBits (Lower Word) Field Descriptions
Bit(s) Name Access Description
[31:0] NumBits (Lower Bits) R Sets bit 31-0 for the NumBits (number of bits received).

This register is the higher word of the 64-bit bit counter snapshot value. The register is reset when the component-reset is asserted or when the RST bit is set to 1.

Table 425.  NumBits (Higher Word) Field Descriptions
Bit(s) Name Access Description
[31:0] NumBits (Higher Bits) R Sets bit 63-32 for the NumBits (number of bits received).

This register is the lower word of the 64-bit error counter snapshot value. The register is reset when the component-reset is asserted or when the RST bit is set to 1.

Table 426.  NumErrors (Lower Word) Field Descriptions
Bit(s) Name Access Description
[31:0] NumErrors (Lower Bits) R Sets bit 31-0 for the NumErrors (number of error bits received).

This register is the higher word of the 64-bit error counter snapshot value. The register is reset when the component-reset is asserted or when the RST bit is set to 1.

Table 427.  NumErrors (Higher Word) Field Descriptions
Bit(s) Name Access Description
[31:0] NumErrors (Higher Bits) R Sets bit 63-32 for the NumErrors (number of error bits received).