Embedded Peripherals IP User Guide

ID 683130
Date 10/18/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

2.4. Parameters

Table 6.  Configurable Parameters
Parameter Legal Values Description
Number of channels 1, 2, 4, 8, and 16 The total number of channels supported on the Avalon® -ST data interfaces.
Symbols per beat 1–32 The number of symbols transferred in a beat on the Avalon® -ST data interfaces
Bits per symbol 1–32 The symbol width in bits on the Avalon® -ST data interfaces.
Error width 0–32 The width of the error signal on the Avalon® -ST data interfaces.
FIFO depth 2–232 The depth of each memory segment allocated for a channel. The value must be a multiple of 2.
Use packets 0 or 1 Setting this parameter to 1 enables packet support on the Avalon® -ST data interfaces.
Use fill level 0 or 1 Setting this parameter to 1 enables the Avalon® -MM status interface.
Number of almost-full thresholds 0 to 2 The number of almost-full thresholds to enable. Setting this parameter to 1 enables Use almost-full threshold 1. Setting it to 2 enables both Use almost-full threshold 1 and Use almost-full threshold 2.
Number of almost-empty thresholds 0 to 2 The number of almost-empty thresholds to enable. Setting this parameter to 1 enables Use almost-empty threshold 1. Setting it to 2 enables both Use almost-empty threshold 1 and Use almost-empty threshold 2.
Section available threshold 0 to 2 Address Width Specify the amount of data to be delivered to the output interface. This parameter applies only when packet support is disabled.
Packet buffer mode 0 or 1 Setting this parameter to 1 causes the core to deliver only full packets to the output interface. This parameter applies only when Use packets is set to 1.
Drop on error 0 or 1 Setting this parameter to 1 causes the core to drop packets at the Avalon® -ST data sink interface if the error signal on that interface is asserted. Otherwise, the core accepts the packet and sends it out on the Avalon® -ST data source interface with the same error. This parameter applies only when packet buffer mode is enabled.
Address width 1–32 The width of the FIFO address. This parameter is determined by the parameter FIFO depth; FIFO depth = 2 Address Width.
Use request Turn on this parameter to implement the Avalon® -MM request interface. If the core is configured to support more than one channel and the request interface is disabled, only channel 0 is accessible.
Use almost-full threshold 1 Turn on these parameters to implement the optional Avalon® -ST almost-full and almost-empty interfaces and their corresponding registers. See Control Interface Register Map for the description of the threshold registers.
Use almost-full threshold 2
Use almost-empty threshold 1
Use almost-empty threshold 2
Use almost-full threshold 1 0 or 1 This threshold indicates that the FIFO is almost full. It is enabled when the parameter Number of almost-full threshold is set to 1 or 2.
Use almost-full threshold 2 0 or 1 This threshold is an initial indication that the FIFO is getting full. It is enabled when the parameter Number of almost-full threshold is set to 2.
Use almost-empty threshold 1 0 or 1 This threshold indicates that the FIFO is almost empty. It is enabled when the parameter Number of almost-empty threshold is set to 1 or 2.
Use almost-empty threshold 2 0 or 1 This threshold is an initial indication that the FIFO is getting empty. It is enabled when the parameter Number of almost-empty threshold is set to 2.