LVDS SERDES Transmitter / Receiver IP Cores User Guide

ID 683062
Date 12/15/2017
Public
Document Table of Contents

1.5.4.4. Setting Timing Constraints Using the TimeQuest Timing Analyzer GUI

Timing constraints for the LVDS receiver are needed only for the input clock ports and the synchronous input ports. The synchronous output ports and the asynchronous input and output ports are set to false path.