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1.1. Features
1.2. Parameter Settings
1.3. Ports
1.4. Prototypes and Component Declarations
1.5. Functional Description
1.6. Simulating Intel® FPGA IP Cores
1.7. Generating ALTLVDS IP Core Using Clear Box Generator
1.8. LVDS SERDES Transmitter/Receiver IP Cores User Guide Archives
1.9. Document Revision History for LVDS SERDES Transmitter/Receiver IP Cores User Guide
1.5.1. Receiver Modes
1.5.2. DPA PLL Calibration
1.5.3. Initialization and Reset
1.5.4. Source-Synchronous Timing Analysis and Timing Constraints
1.5.5. Arria II GX, Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V LVDS Package Skew Compensation Report Panel
1.5.6. ALTLVDS IP Core in External PLL Mode
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1.5.4.3.2. Obtaining the TCCS Report
For LVDS transmitters, the TimeQuest Timing Analyzer provides a TCCS report, which shows TCCS values for serial output ports.
To obtain the TCCS report (report_TCCS), follow these steps:
- In the Intel® Quartus® Prime software, under the Tools menu, click TimeQuest Timing Analyzer.
- From the TimeQuest Timing Analyzer, under Reports, select Device Specific and click Report TCCS.