• Updated the topic listing the PLL clock signals for the LVDS interface in external PLL mode to specify that the pll_areset signal is only available in external PLL mode if your turn on the DPA.
• Rebranding for Intel.

• Added Intel® Cyclone® 10 LP support.
• Renamed "Quartus II" to "Quartus Prime".
• Removed topics about the installing and licensing IP cores, IP catalog and parameter editor, customizing and generating IP cores, files generated for the IP cores, and upgrading IP cores, and added a link to Introduction to Intel FPGA IP Cores.
• Updated and added links to related information.

• Updated the topic that lists the features of the IP cores to clarify that these IP cores are not available for the Intel® Stratix® 10 and Intel® Arria® 10 devices.
• Added recommendation to assert the rx_data_reset signal synchronous to the rx_syncclock signal.

• Added footnotes to clarify the availability of DPA and soft-CDR modes in Stratix series.
• Removed Cyclone series from the list of series with soft-CDR support.
• Added guidelines about the time required for tx_outclock to stabilize if you turn on the Implement Deserializer circuitry in logic cells option.
• Updated the statement that refers to selecting "Left/Right PLL" to set up PLL in LVDS mode to clarify that the option is required only for Arria II devices.
• Updated information about the PLL IP core to clarify that for Stratix IV, Arria II, and Cyclone IV devices, the PLL IP core is ALTPLL IP, and for Stratix® V, Arria V, and Cyclone V devices, the PLL IP core is Altera PLL.

• Restructured and updated sections that describe the external PLL mode and the relevant ALTPLL IP core parameters.
  • Added recommendations about getting the correct ALTPLL phase shift and duty cycle values for the external PLL mode.
  • Clarified that the rx_syncclock is automatically created by the Quartus II software only when it is required.
• Updated the ALTLVDS_RX ports list to clarify that the rx_cda_reset port is not supported in Arria V and Cyclone V devices. In these devices, use the rx_channel_data_align signal instead.

• Replaced MegaWizard Plug-In Manager information with IP Catalog.
• Added standard information about upgrading IP cores.
• Added standard installation and licensing information.
• Removed outdated device support level information. IP core device support is now available in IP Catalog and parameter editor.
• Updated a statement about valid data availability for rx_channel_data_align signal in the topic about ALTLVDS_RX parameter settings.

• outclock_alignment: clarify that this parameter is only used by the RTL simulation model and has no affect on how the Fitter sets the PLL parameters.
• outclock_phase_shift: clarified that this parameter is used to set the phase shift parameters used by the PLL.

Updated the following parameters:

• inclock_data_alignment: clarified that this parameter is only used by the RTL simulation model and has no affect on how the Fitter sets the PLL parameters.
• inclock_phase_shift: clarified that this parameter is used to set the phase shift parameters used by the PLL.

• Removed Use clock pin parameter. This parameter is no longer available for the megafunction beginning from ACDS 13.0.
• Updated Table 1 to include Arria V, Arria V GZ, and Stratix® V device family support. Also added a note to clarify that Altera recommends implementing the Bus LVDS (BLVDS) I/O with user logic, instead of the ALTLVDS_TX and ALTLVDS_RX megafunctions.
• Updated Table 5 and Table 6 to remove Stratix® V device family support and to clarify that In Cyclone series, except Cyclone V, the SERDES is always implemented in logic cells for the Implement Deserializer circuitry in logic cells option.
• Updated Table 5 to clarify that the values for the What is the phase alignment of 'tx_in' with respect to the rising edge of 'tx_inclock'? (in degrees) option is device dependent.
• Updated Table 5 and Table 6 to remove Stratix® V device family support for the Enable self-reset on lost lock in PLL, Enable PLL Calibration, and Use 'dpa_pll_recal' input port options.
• Updated Table 6 to add Arria V and Arria V GZ devices support for the Enable Dynamic Phase Alignment mode, Use 'rx_divfwdclk' output port and bypass the DPA FIFO, Use 'rx_dpa_locked' output port, Use a DPA initial phase selection of, and Align DPA to rising edge of data only options.
• Updated Table 6 to clarify that the values for the What is the phase alignment of 'rx_in' with respect to the rising edge of 'rx_inclock'? option is device dependent.
• Updated Table 6 to add the Is this interface constrained to the left, or right banks? option.
• Updated to add Arria V and Arria V GZ devices support for common_rx_tx_pll.
• Updated to remove Stratix® V device family support for the deserialization_factor, use_no_phase_shift, use_external_pll, and pll_self_reset_on_loss_lock ( Stratix® V devices do not support SERDES using logic cells).
• Updated to add Arria V and Arria V GZ devices support for deserialization_factor.
• Updated to add Arria V and Arria V GZ devices support for inclock_data_alignment, outclock_divide_by, outclock_duty_cycle, outclock_resource, registered_input, and use_external_pll.
• Updated to add Arria V, Arria V GZ, Cyclone V, and Stratix® V devices.

• Updated Standard Mode on page 47 to add a note to recommend using rx_divfwdclk (instead of any static clock) as the SignalTap capturing clock.
• Updated Receiver Skew Margin and Transmitter Channel-to- Channel Skew on page 54 to fix the error in RSKM equation by replacing TCCS with RCCS. Also added information on how to apply the RCCS figure to the RSKM calculation in TimeQuest.
• Updated Arria II GX, Arria V, Arria V GZ, Cyclone V, and Stratix® V LVDS Package Skew Compensation Report Panel on page 61 to add Arria V, Arria V GZ, and Cyclone V devices.
• Updated Figure 2 to fix the waveform error for c1 (288 degrees phase shift)
• Updated tx_enable and rx_enable ports inTable 11 and Table 10 to clarify that the Set up PLL in LVDS mode option and the enable0 and enable1 ports are only for Stratix II devices.
• Updated Parameters Used by the ALTPLL Megafunction.
• Added a link to the High-Speed Differential I/O Interfaces and DPA in Arria V Devices.

• Updated Table 2-2 on page 2-7 to fix content error for the What is the deserialization factor? and Use 'rx_dpa_locked' output port options.
• Updated "Clock Forwarding" on page 3-1.
• Updated "DPA PLL Calibration" on page 3-4 to fix device family support.
• Updated "Dedicated SERDES" on page 3-9 to add a note on TimeQuest Timing Analyzer.
• Updated Table 3-5 on page 3-25 to update description for rx_in[]and rx_inclock.
• Updated Table 3-6 on page 3-28 to update description for tx_inclock and tx_out[].

• Updated "Source-Synchronous Timing Analysis and Timing Constraints" section.
• Added design examples.
• Updated "Parameter Settings" chapter to include "Use Clock Pin" parameter.

• Reorganized the document format.
• Added "Source-Synchronous Timing Analysis and Timing Constraints" section.
• Added "Generating Clock Signals for LVDS Interface" section.
• Updated the timing diagram in the "Receiver Skew Margin and Transmitter Channel-to-Channel Skew" section.
• Updated "Parameter Settings" chapter.
• Added "Using Clear Box Generator" section.

• Updated "DPA PLL Calibration in Stratix III and Stratix IV E Devices" section.
• Added Verilog HDL prototypes.
• Added VHDL LIBRARY-USE declaration.
• Added VHDL Component Declarations.
• Added new ports and parameters.
• Added new parameter settings.
• Removed Design Examples for this release.

• Added "Device Support".
• Updated "Specifications" section to include "Ports and Parameters in ALTLVDS_RX Megafunction" and "Ports and Parameters in ALTLVDS_TX Megafunction".
• Added "Specifications".

• Updated Table 4, and Table 12.
• Added DPA Misalignment Issue, Figure 3, and "DPA PLL Calibration", Figure 20 and Figure 21.
• Added Table 11 ALTLVDS Receiver DPA settings 3 option (page 7) and Table 19 Configuration Settings for Design Example 4 (LVDS Receiver).
• Added description about "Design Example 4: Stratix III ALTLVDS Receiver with DPA PLL Calibration.

• Removed figures.
• Added Stratix IV to Device Family Support.
• Updated Table 3, Table 4, Table 5, Table 6, Table 7, Table 8, Table 12, Table 13, Table 15,Table 3-1, Table 3-2, Table 3-3, Table 3-4, and Table 3-6.
• Added Enable bitslip control, Enable independent bitslips controls for each channel, and Register the bitslip control input using 'rx_outclock' parameters and descriptions Table 11.
• Updated steps in Functional Results-Simulate the ALTLVDS Receiver/Transmitter Design in the ModelSim-Altera Software, Functional Results-Simulate the ALTLVDS Receiver/Transmitter Design in the Quartus II Software, "Functional Results-Simulatethe ALTLVDS Receiver/Transmitter Design in the ModelSim-Altera Software".
• Added tx_syncclock and descriptions in Table 3-1.
• Added rx_data_align and rx_syncclock in Table 3-4.
• Updated descriptions in Table 3-6.

• Added soft-CDR mode.
• Added description of new receiver output port rx_divfwdclk[].
• Added description of new receiver parameters enable_soft_cdr, is_negative_ppm_drift,net_ppm_variation, enable_dpa_align_to_ rising_edge_only, dpa_initial_phase_ value, and enable_dpa_initial_phase _selection.
• Updated two design examples.
• Added third design example using soft-CDR mode.