LVDS SERDES Transmitter / Receiver IP Cores User Guide

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ID 683062
Date 12/15/2017
Public
Document Table of Contents
Document Table of Contents x
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide x
1.1. Features 1.2. Parameter Settings 1.3. Ports 1.4. Prototypes and Component Declarations 1.5. Functional Description 1.6. Simulating Intel® FPGA IP Cores 1.7. Generating ALTLVDS IP Core Using Clear Box Generator 1.8. LVDS SERDES Transmitter/Receiver IP Cores User Guide Archives 1.9. Document Revision History for LVDS SERDES Transmitter/Receiver IP Cores User Guide
1.1. Features x
1.1.1. Resource Utilization and Performance
1.2. Parameter Settings x
1.2.1. ALTLVDS_TX Parameter Settings 1.2.2. ALTLVDS_RX Parameter Settings 1.2.3. Command Line Interface Parameters
1.3. Ports x
1.3.1. ALTLVDS_TX Ports 1.3.2. ALTLVDS_RX Ports
1.4. Prototypes and Component Declarations x
1.4.1. Verilog HDL Prototype 1.4.2. VHDL Component Declaration 1.4.3. VHDL LIBRARY-USE Declaration
1.5. Functional Description x
1.5.1. Receiver Modes 1.5.2. DPA PLL Calibration 1.5.3. Initialization and Reset 1.5.4. Source-Synchronous Timing Analysis and Timing Constraints 1.5.5. Arria II GX, Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V LVDS Package Skew Compensation Report Panel 1.5.6. ALTLVDS IP Core in External PLL Mode
1.5.1. Receiver Modes x
1.5.1.1. DPA Mode 1.5.1.2. Non-DPA Mode 1.5.1.3. Soft-CDR Mode
1.5.1.3. Soft-CDR Mode x
1.5.1.3.1. Clock Forwarding 1.5.1.3.2. Standard Mode 1.5.1.3.3. No Output Register Mode
1.5.2. DPA PLL Calibration x
1.5.2.1. DPA PLL Calibration in Stratix IV ES Devices 1.5.2.2. DPA PLL Calibration in Arria II and Stratix IV Devices and Later 1.5.2.3. Effects of DPA PLL Calibration
1.5.3. Initialization and Reset x
1.5.3.1. Initializing ALTLVDS_TX and ALTLVDS_RX 1.5.3.2. Resetting the DPA 1.5.3.3. Aligning the Word Boundaries 1.5.3.4. Recommended Initialization and Reset Flow
1.5.4. Source-Synchronous Timing Analysis and Timing Constraints x
1.5.4.1. Dedicated SERDES 1.5.4.2. SERDES in LEs 1.5.4.3. Receiver Skew Margin and Transmitter Channel-to-Channel Skew 1.5.4.4. Setting Timing Constraints Using the TimeQuest Timing Analyzer GUI 1.5.4.5. Setting Timing Constraints Manually in the Synopsys Design Constraint File
1.5.4.3. Receiver Skew Margin and Transmitter Channel-to-Channel Skew x
1.5.4.3.1. Obtaining the RSKM Report 1.5.4.3.2. Obtaining the TCCS Report
1.5.4.4. Setting Timing Constraints Using the TimeQuest Timing Analyzer GUI x
1.5.4.4.1. Constraining the Input Clock Signal
1.5.6. ALTLVDS IP Core in External PLL Mode x
1.5.6.1. PLL Clock Signals for LVDS Interface in External PLL Mode 1.5.6.2. External PLL Compensation Mode for ALTLVDS IP Core in External PLL Mode
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide

To constrain the input clock signal in the TimeQuest Timing Analyzer, follow these steps:

  1. Run full compilation for the LVDS design. Ensure that the timing analysis tool is set to TimeQuest Timing Analyzer.
  2. After full compilation completes, on the Tools menu, select TimeQuest Timing Analyzer to launch the TimeQuest analyzer window.
  3. In the Tasks list, under Diagnostic, click Report Unconstrained Paths to view the list of unconstrained paths and ports of the LVDS design.
  4. In the Report list, under Unconstrained Paths, click Clock Status Summary to view the clock that requires constraints. The default setting for all unconstrained clocks is 1 GHz. To constrain the clock signal, right-click the clock name and select Edit Clock Constraint.
  5. In the Create Clock dialog box, set the period and the clock rising and falling edge (duty cycle of the clock) constraint. Refer to Table 1 for timing constraints options and descriptions.
  6. Click Run.

Constraining the Synchronous Input Ports

Constrain the synchronous input signals for non-DPA mode SERDES to allow the TimeQuest Timing Analyzer to consider your board channel-to-channel skew in the RSKM report. Without these constraints, you need to subtract the board channel-to-channel skew from the RSKM value reported by the TimeQuest Timing Analyzer.

To constrain the synchronous input signals in the TimeQuest Timing Analyzer, follow these steps:

  1. Run full compilation for the LVDS design. Ensure that the timing analysis tool is set to TimeQuest Timing Analyzer.
  2. After full compilation completes, on the Tools menu, select TimeQuest Timing Analyzer to launch the TimeQuest analyzer window.
  3. In the Tasks list, under Diagnostic, double-click Report Unconstrained Paths to view the list of unconstrained paths and ports of the LVDS design.
  4. In the Report list, under Unconstrained Paths category, expand the Setup Analysis folder, and then click Unconstrained Input Ports.
  5. Set constraints for all the receiver synchronous input ports in the From list. To set input delay, perform the following steps:
    1. Right-click on the synchronous input port and select Set Input Delay.
    2. The Set Input Delay dialog box appears.
    3. Select the desired clock using the pull down menu. The clock name must reference the source synchronous clock that feeds the LVDS receiver.
    4. Set the appropriate values for Input Delay and Delay. Refer to Table 1 for timing constraints options and descriptions.
    5. Click Run to incorporate these values in the TimeQuest Timing Analyzer.
If no input delay is set in the TimeQuest Timing Analyzer, the receiver channel-to-channel skew (RCCS) defaults to zero.

Setting False Path for the Asynchronous Input and Output Ports

All asynchronous input and output ports are excluded from the timing analysis of the LVDS core because the signals on these ports are not synchronous to a IP core clock source. The internal structure of the LVDS IP core handles the metastability of these asynchronous signals. Therefore these asynchronous signals are set to false path.

To exclude asynchronous input and output ports from the timing analysis, perform the following steps:

  1. Run full compilation for the LVDS design. Ensure that the timing analysis tool is set to TimeQuest Timing Analyzer.
  2. After full compilation completes, on the Tools menu, select TimeQuest Timing Analyzer to launch the TimeQuest analyzer window.
  3. In the Tasks list, under Diagnostic, double-click Report Unconstrained Paths to view the list of unconstrained paths and ports of the LVDS design.
  4. In the Report list, under Unconstrained Paths category, expand the Setup Analysis folder.
  5. Click Unconstrained Input Port Paths to view the unconstrained input ports or click Unconstrained Output Port Paths to view the unconstrained output ports.
  6. Right-click on an ansynchronous input or output port, and select Set False Path.

After you specify all timing constraint settings for the clock signal, on the Constraints menu, click Write SDC File to write all the constraints to a specific .sdc. Then, run full compilation for the LVDS design again.

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