1.2.2. ALTLVDS_RX Parameter Settings
On the General page (page 3) of the parameter editor, depending on the device you selected, you can configure the following options:
- Implement the SERDES circuitry in LEs (logic cells) or dedicated SERDES
- Use internal PLL or external PLL
- Use DPA mode or non-DPA mode
The selections you make on the General page determine the features available on the remaining pages of the parameter editor.
The following table lists the parameter settings for the LVDS receiver IP core.
| Option | Description |
|---|---|
| General (page 3) | |
| Implement Deserializer circuitry in logic cells | Turn on this option to implement the SERDES circuitry in logic cells. The receiver starts its operation on the first fast clock edge after the PLL is locked. This option is intended for slow speeds. The byte alignment may be different from the hard SERDES implementation. Turn off this option to use the dedicated SERDES circuitry in the device. This option is supported in Arria® GX, Arria® II GX, Arria® II GZ, HardCopy® II, HardCopy® III, HardCopy® IV, Stratix, Stratix GX, Stratix II, Stratix II GX, Stratix III, and Stratix IV devices. In Cyclone® series, except Cyclone® V devices, the SERDES is always implemented in logic cells. Cyclone® V devices contain dedicated SERDES circuitry. |
| Enable Dynamic Phase Alignment mode | Turn on this option to correct the skews created by the different trace lengths on the data channels routed to the device. This mode adds several ports and parameters to the IP core instances. This option is available for Arria® GX, Arria® II GX, Arria® II GZ, Arria® V, Arria® V GZ, HardCopy® II, HardCopy® III, HardCopy® IV, Stratix, Stratix GX, Stratix II, Stratix II GX, Stratix III, Stratix IV, and Stratix® V devices only. Enabling the DPA mode changes the appearance of the graphic representation of the IP core in the left-hand pane. When you turn on the DPA mode, additional ports and parameters are added to the IP core. Depending on the selected device, the following pages are added to the parameter editor to include the additional DPA mode settings:
|
| What is the number of channels? | The number DPA settings 3of input channels available for the LVDS receiver. If the required number of channels is not available in the list, type the desired number in this box. For example, if the number of channels is 44, the port created is tx_out[43..0]. The legal values depend on the pins available in the device. For the legal values available for your device, refer to the relevant device handbook. |
| What is the deserialization factor? | Determines the number of serial input data bits that the receiver deserializes and sends to the core on a single cycle. For the valid deserialization factors for your device, refer to the relevant device handbook. For example, if the deserialization factor is 10 and the number of input channels is 1, the receiver deserializes every 10 serial bits into 10 bits of parallel data to send to the core. If the deserialization factor is 10 and the number of channels is 44, the port created is rx_out[439..0]. |
| Use External PLL | Turn on this option to use an external PLL to clock the SERDES receiver. When you turn on this option, the options on the Frequency/PLL settings page are disabled. You must use a separate PLL to provide the clocking source and make the necessary connections. You must ensure your circuit has the correct input and functionality to generate an appropriate clock frequency and is correctly connected to the LVDS receiver. When you have a deserialization factor of two, the IP core bypasses the SERDES and implements the SERDES functionality in DDR registers. A deserialization factor of at least four is required to use the external PLL option. If you turn off this option, the IP core automatically implements an internal PLL to clock the ALTLVDS_RX block. For Stratix and Stratix GX devices, if you implement SERDES for your LVDS transmitter using a dedicated SERDES block, you do not have the option to use an external PLL. |
| Use 'rx_data_reset' input port | This option is enabled when you implement the LVDS in logic cells. Turn on this option to add an input port to the IP core. When the input port asserts, the IP core asynchronously resets all the logic in the ALTLVDS_RX IP core excluding the PLL. Intel recommends that you assert the rx_data_reset signal synchronous to the rx_syncclock signal. |
| Is this interface constrained to the left, or right banks? | Turn on this option if the LVDS interface is constrained to the left or right IO banks. This option determines the PLL compensation mode in Cyclone® V devices. |
| Frequency/ PLL Settings (page 4) The options on this page are available only when you are using internal PLL |
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| What is the input data rate? | Specifies the data rate for the input channel of the receiver, in Mbps. For data rate ranges, refer to the specific Device Data Sheet chapter in the respective device handbook. This value determines the legal input clock rate values. |
| Specify input clock rate by | Specifies the clock frequency (rx_inclock) and the clock period (inclock_period) for the internal PLL. The legal values depend on the output data rate selected. |
| Use shared PLL(s) for receivers and transmitters | When you turn on this option, your LVDS receivers and transmitters can share the same PLL. Turn on this option when the LVDS receivers and transmitters use the same input clock frequency, deserialization factor, and data rates. |
| Use 'pll_areset' input port | Turn on this option to control the asynchronous reset port of the PLL that the IP core uses with this function. When other ALTLVDS blocks share the PLL with the receiver and use the pll_areset port, you must use this port in all IP core instantiations and tie the signals together in the design file. If you use the pll_areset port only in one IP core instance, the PLLs are not shared, and a warning appears during compilation. The PLL must be reset to set the output clock phase relationships correctly when the PLL loses lock, or if the PLL input reference clock is not stable when the device completes the configuration process. |
| Use 'rx_pll_enable' input port | Turn on this option to control the enable port of the fast PLL that the IP core uses with this function. If the receiver shares the PLL with other ALTLVDS blocks, and uses the rx_pll_enable port, you must use this port in all IP core instances and tie the signal together in the design file. If you use the rx_pll_enable port only in one IP core instance, the PLLs are not shared and a warning appears during compilation. |
| Use 'rx_locked' output port | Turn on this option to monitor the lock status of the PLL. The status of the lock port is identical for the transmitter and the receiver when the IP cores use shared PLLs. In this case, monitor the lock output from the receiver IP core. |
| What is the clock resource used for 'rx_outclock'? | Specifies the clock resource type fed from the rx_outclock port. Legal values are Auto selection (the Compiler determines the type), Global clock, and Regional clock. The default value is Auto selection. |
| What is the phase alignment of 'rx_in' with respect to 'rx_inclock'? | Determines the phase alignment of the data that the receiver core receives with respect to the rx_inclock signal. Available values are 0.00, 22.50, 45.00, 67.50, 90.00, 112.50, 135.00, 157.50, 180.00, 202.50, 225.00, 247.50, 270.00, 292.50, 315.00, and 337.50. The values for this option are device dependent. This option is only available if you turn off the DPA mode. |
| Use source-synchronous mode of the PLL | Turn on this option to ensure that the IP core instance makes the required phase adjustment to guarantee a consistent relationship between the clock and the data, at the capture register and at the pin. Always turn on this option, unless you have performed all of the necessary phase adjustments manually. Intel recommends that you turn on this option when you use non-dedicated SERDES schemes. This option is only available when you implement the SERDES in LEs. |
| Align clock to center of data window at capture point | Turn on this option to add a phase shift of 90° to the clock, which center-aligns the clock in the data. This option is only available for Arria® GX, Cyclone® II, Stratix II GX, Stratix II, and HardCopy® II devices when you implement the SERDES in logic cells. |
| Enable self-reset on lost lock in the PLL | Turn on this option to reset the PLL automatically when the PLL loses lock. This option is only available for Arria® II GX, Arria® II GZ, HardCopy® III, HardCopy® IV, Stratix III, Stratix IV, Cyclone® III, Cyclone® IV, and Intel® Cyclone® 10 LP devices when you implement the SERDES in logic cells. |
| Enable FIFO for DPA channels | The phase-compensation FIFO buffer synchronizes parallel data to the global clock domain of the core. This option is only available in Stratix GX devices when you turn on the DPA mode. |
| DPA Settings 1 (page 5) The options on this page are available when you turn on the DPA mode. |
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| Use 'rx_divfwdclk' output port and bypass the DPA FIFO | Turn on this option to divide the DPA clock by the deserialization factor and then forward the DPA clock to the core. The DPA clock drives the bit-slip and alignment circuitry, bypassing the FIFO. Turn on this option for soft-CDR mode. This option is available in Arria® II GX, Arria® II GZ, Arria® V, Arria® V GZ, HardCopy® III, HardCopy® IV, Stratix III, Stratix IV, and Stratix® V devices only. |
| What is the simulated recovered clock phase drift? | Models a phase drift in the recovered clock. Clock phase drift is expressed as the equivalent number of full clock cycles of drift for every parts per million (PPM) clock cycles. The value for this option can be positive, negative or zero. |
| Use 'rx_dpll_enable' input port | Enables the path through the DPA circuitry. The option supports dynamic, channel-by-channel control of the DPA circuitry. To enable the DPA circuitry for a channel, set the port for the target channel to 1. If this port is not used, the Intel® Quartus® Prime software enables all of the channels. |
| Use 'rx_dpll_hold' input port | Prevents the DPA circuitry from switching to a new clock phase on the target channel. Each DPA block monitors the phase of the incoming data stream continuously and selects a new clock phase when needed. When this port is held high, the selected channels hold their current phase setting. |
| Use 'rx_fifo_reset' input port | Resets the FIFO buffer between the DPA circuit and the data alignment circuit. The FIFO buffer holds the data passing between the DPA and the LVDS clock domains. When this port is held high, the FIFOs in the selected channels are reset. This option is available only if you turn off the Use 'rx_divfwdclk' output port and bypass the DPA FIFO option. |
| DPA Settings 2 (page 6) The options on this page are available when you turn on the DPA mode. |
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| Use 'rx_reset' input port | Resets all components of the DPA circuit. You must retrain the DPA circuit after this port resets the DPA circuitry. |
| Automatically reset the bit serial FIFO when 'rx_dpa_locked' rises for the first time | Specifies when the bit-serial FIFO resets for DPA circuit. This option is only available in Stratix II, Arria® GX, and HardCopy® II devices. |
| User explicitly resets the bit serial FIFO through 'rx_reset' | When you turn on the rx_reset port, the ALTLVDS_RX parameter editor allows you to choose whether or not to automatically reset the bit-serial FIFO when rx_dpa_locked signal rises for the first time. This is a useful feature because it keeps the synchronizer FIFO in reset until the DPA locks. This option is only available in Stratix II, Arria® GX, and HardCopy® II devices. |
| Use 'rx_dpa_locked' output port | The DPA block samples the data on one of eight phase clocks with a 45° resolution between phases. This port lets you monitor the status of the DPA circuit and determine when it has locked onto the phase closest to the incoming data phase. The rx_dpa_locked port behaves differently for various device families. After the IP core asserts the rx_dpa_locked signal is upon initial lock, the rx_dpa_locked signal does not deassert in Arria® V, Arria® V GZ, Stratix III, Stratix IV, Stratix® V, HardCopy® III, HardCopy® IV, and Arria® II GX unless explicitly reset using rx_reset or rx_dpa_lock_reset. In Stratix GX, Stratix II, HardCopy® II, and Arria® GX, the rx_dpa_locked signal toggles depending on how the next two settings are selected. After power up or reset, the rx_dpa_locked signal is asserted after the DPA circuitry acquires an initial lock to the optimum phase. You must not use the rx_dpa_locked signal to validate the integrity of the LVDS link. Use error checkers (for example, CRC or DIP4) to validate the integrity of the LVDS link. The rx_dpa_locked signal is not supported when using non-DPA mode or soft-CDR mode. |
| When phase alignment circuitry switches to a new phase | DPA deasserts when the phase alignment circuitry switches to a new phase. This option is only available in Stratix II, HardCopy® II, and Arria® GX devices. |
| When there are two phase changes in the same direction | The rx_dpa_locked signal deasserts after the DPA switches two phases in the same direction. This option is only available in Stratix II, HardCopy® II, and Arria® GX devices. |
| Use 'rx_dpa_lock_reset' input port | Resets the DPA lock circuitry. |
| Use a DPA initial phase selection of | Turn on this option to select the initial phase setting. Specifies whether to turn on this option and its value. Simulation honors this phase selection in simulating the forwarded clock. This option is available for Arria® II GX, Arria® II GZ, Arria® V, Arria® V GZ, HardCopy® III, HardCopy® IV, Stratix III, Stratix IV, and Stratix V devices only. |
| Align DPA to rising edge of data only | Turn on this option to align the DPA to the rising edge of the data only or turn of this option to align the DPA to both the rising and falling edges of the data. This option is available for Arria® II GX, Arria® II GZ, HardCopy® III, HardCopy® IV, Stratix III, Stratix IV, and Stratix® V devices only. |
| DPA Settings 3 (page 7) The options on this page are available when you turn on the DPA mode. |
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| Enable PLL Calibration | Turn on this option to phase-shift the PLL outputs when the dpa_pll_cal_busy signal is high. The default setting is OFF. This option is available for Arria® II GZ, HardCopy® III, HardCopy® IV, Stratix III, and Stratix IV devices only. When you enable PLL calibration, you cannot merge the PLL with other PLLs. |
| Use 'dpa_pll_recal' input port | This port recalibrates the PLL without resetting the DPA. This option is available for Arria® II GZ, HardCopy® III, HardCopy® IV, Stratix III, and Stratix IV devices only. |
| What is the input data rate? | Specifies the data rate for the input channel of the receiver, in Mbps. For data rate ranges, refer to the specific Device Data Sheet chapter in the respective device handbook. This value determines the legal input clock rate values. |
| Receiver Settings (page 8) | |
| Register outputs | Turn on this option to implement soft-CDR receiver modes in standard mode. In standard mode, the outputs of the receiver are registered by the rx_outclock signal. Turn off this option if you do not want to register the receiver outputs. In no output register mode, you must register the output registers in the design logic that is fed by the receiver, and then specify a Source Multiply assignment from the receiver to the output registers with a value equal to the deserialization factor. |
| Use 'rx_cda_reset' input port | The port resets the data alignment circuitry, restoring the latency bit counter to zero. This option is available only if you turn on the Use 'rx_channel_data_align' input port option. This option is available only if you use dedicated SERDES block. |
| Use 'rx_cda_max' output port | Indicates when the rollover point is reached in the data alignment circuit. This port is available only if you turn on the Use 'rx_channel_data_align' input port option. This option is available only if you use a a dedicated SERDES block. |
| After how many pulses does the data alignment circuitry restore the serial latency back to 0? | Specifies, in pulses, when the DPA circuitry restores the serial data latency to 0. The value does not have to be the same as the deserialization factor, but set the value to the deserialization factor to make the rollover occur for every deserialization factor. The available values for this option range from 1 to 11. This option is available only if you use a dedicated SERDES block. |
| Align data to the rising edge of clock | When you turn on this option, the data path is registered on the positive edge of the diffioclk signal (also referred to as the LVDS clock). When you turn off this option, the data path is registered on the negative edge of the diffioclk signal. This option is available only if you use a dedicated SERDES block, and is available only in non-DPA mode. This option changes the phase that captures the received data by 180°. Use caution when you turn off this option. The phase shift of the capture clock is automatically set according to the setting for the What is the phase alignment of 'rx_in' with respect to the rising edge of 'rx_inclock'? (in degrees) option. Changing the phase of the capture clock can lead to data corruption. If you turn off this option, the LVDS data is aligned to the falling edge of the clock. For an example, if you have two receivers interface with identical parameters except for the rx_in signal relationship to the rx_inclock signal, and you want to merge PLLs, one interface must have a 0° (rising edge) alignment, and the second interface must have a 180° (falling edge) alignment. You can only merge the PLLs when they have the same clock and phase settings; both must be set with the same alignment. You can set both receivers to be 0° aligned, and turn off Align data to the rising edge of clock on the 180° aligned interface. |
| Use 'rx_coreclk' input port | This option is enabled when the LVDS is implemented in logic. When you turn on this option, it adds an input port, which when asserted performs an asynchronous reset of all the logic in the ALTLVDS_RX IP core excluding the PLL. |
| Use 'rx_channel_data_align' input port | Turn on this option to control bit insertion on a channel-by-channel basis to align the word boundaries of the incoming data. The data slips one bit for every pulse on the rx_channel_data_align port. This option is available only if you use a dedicated SERDES block. You can use control characters in the data stream so your logic can have a known pattern to search for. You can compare the data received for each channel, compare to the control character you are looking for, then pulse the rx_channel_data_align port as required until you successfully receive the control character. To use this port, you must meet the following requirements:
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| Enable independent bitslip controls for each channel | Turn on this option to allow an independent rx_data_align signal for each channel that independently control the bit slip capability of each channel. This option is available if you implement the SERDES in LEs. |
| Add extra register for 'rx_data_align' input port | Turn on this option to enable the synchronization register of the receiver. If you turn on this option, you can also add an extra register to register the rx_data_align port using the rx_outclock port. This option is available if you implement the SERDES in LEs. |
| Use 'rx_data_align_reset' input port | Turn on this option to create the reset port for the bit-slip circuitry. This option is available if you implement the SERDES in LEs. |
| Which output synchronization buffer implementation should be used? | Specifies where to implement the buffer. The values are Use RAM Buffer, Use Multiplexer and synchronization register, and Use logic element based RAM buffer. A value of Use Multiplexer and synchronization register implements a multiplexer instead of a buffer. A value of Use RAM Buffer implements a buffer in RAM blocks. A value of Use logic element based RAM buffer implements a buffer in logic elements. The Use RAM Buffer and Use logic element based RAM buffer values use more logic, but result in the correct word alignment. If omitted, the default value is Use RAM Buffer. |
| Simulation Model (page 9) | |
| Simulation Libraries | Specifies the libraries needed for functional simulation by third-party tools. |
| Generate netlist | Turn on this option to generate synthesis area and timing estimation netlist. |
| Summary (page 10) | |
| Summary | Specifies the types of files to be generated. A gray checkmark indicates a file that is automatically generated; a green checkmark indicates an optional file. Choose from the following types of files:
If you turn on the Generate netlist option, the file for that netlist is also available (<function name> _syn.v). |