LVDS SERDES Transmitter / Receiver IP Cores User Guide

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ID 683062
Date 12/15/2017
Public
Document Table of Contents
Document Table of Contents x
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide x
1.1. Features 1.2. Parameter Settings 1.3. Ports 1.4. Prototypes and Component Declarations 1.5. Functional Description 1.6. Simulating Intel® FPGA IP Cores 1.7. Generating ALTLVDS IP Core Using Clear Box Generator 1.8. LVDS SERDES Transmitter/Receiver IP Cores User Guide Archives 1.9. Document Revision History for LVDS SERDES Transmitter/Receiver IP Cores User Guide
1.1. Features x
1.1.1. Resource Utilization and Performance
1.2. Parameter Settings x
1.2.1. ALTLVDS_TX Parameter Settings 1.2.2. ALTLVDS_RX Parameter Settings 1.2.3. Command Line Interface Parameters
1.3. Ports x
1.3.1. ALTLVDS_TX Ports 1.3.2. ALTLVDS_RX Ports
1.4. Prototypes and Component Declarations x
1.4.1. Verilog HDL Prototype 1.4.2. VHDL Component Declaration 1.4.3. VHDL LIBRARY-USE Declaration
1.5. Functional Description x
1.5.1. Receiver Modes 1.5.2. DPA PLL Calibration 1.5.3. Initialization and Reset 1.5.4. Source-Synchronous Timing Analysis and Timing Constraints 1.5.5. Arria II GX, Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V LVDS Package Skew Compensation Report Panel 1.5.6. ALTLVDS IP Core in External PLL Mode
1.5.1. Receiver Modes x
1.5.1.1. DPA Mode 1.5.1.2. Non-DPA Mode 1.5.1.3. Soft-CDR Mode
1.5.1.3. Soft-CDR Mode x
1.5.1.3.1. Clock Forwarding 1.5.1.3.2. Standard Mode 1.5.1.3.3. No Output Register Mode
1.5.2. DPA PLL Calibration x
1.5.2.1. DPA PLL Calibration in Stratix IV ES Devices 1.5.2.2. DPA PLL Calibration in Arria II and Stratix IV Devices and Later 1.5.2.3. Effects of DPA PLL Calibration
1.5.3. Initialization and Reset x
1.5.3.1. Initializing ALTLVDS_TX and ALTLVDS_RX 1.5.3.2. Resetting the DPA 1.5.3.3. Aligning the Word Boundaries 1.5.3.4. Recommended Initialization and Reset Flow
1.5.4. Source-Synchronous Timing Analysis and Timing Constraints x
1.5.4.1. Dedicated SERDES 1.5.4.2. SERDES in LEs 1.5.4.3. Receiver Skew Margin and Transmitter Channel-to-Channel Skew 1.5.4.4. Setting Timing Constraints Using the TimeQuest Timing Analyzer GUI 1.5.4.5. Setting Timing Constraints Manually in the Synopsys Design Constraint File
1.5.4.3. Receiver Skew Margin and Transmitter Channel-to-Channel Skew x
1.5.4.3.1. Obtaining the RSKM Report 1.5.4.3.2. Obtaining the TCCS Report
1.5.4.4. Setting Timing Constraints Using the TimeQuest Timing Analyzer GUI x
1.5.4.4.1. Constraining the Input Clock Signal
1.5.6. ALTLVDS IP Core in External PLL Mode x
1.5.6.1. PLL Clock Signals for LVDS Interface in External PLL Mode 1.5.6.2. External PLL Compensation Mode for ALTLVDS IP Core in External PLL Mode
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide

1.5.4.5. Setting Timing Constraints Manually in the Synopsys Design Constraint File

You can also set timing constraints manually using SDC commands in an .sdc, and include the .sdc into your Intel® Quartus® Prime design file.

The following example shows a simple source-synchronous interface coding, where the data is aligned with respect to the falling edge of the clock. 

#**************************************************************
# Create Clock
#**************************************************************
create_clock -name virtual_clock_lvds -period 25
create_clock -name {rx_inclock} -period 25.000 -waveform { 0.000 12.500
} [get_ports {rx_inclock}] -add
#**************************************************************
# Create Generated Clock
#**************************************************************
derive_pll_clocks 
**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -clock [get_clocks virtual_clock_lvds] -clock_fall -max 
0.200 [get_ports rx_in*] -add_delay
set_input_delay -clock [get_clocks virtual_clock_lvds] -clock_fall -min 
-0.200 [get_ports rx_in*] -add_delay

To add the .sdc into your Intel® Quartus® Prime design file, follow these steps:

  1. In the Intel® Quartus® Prime software, click on the Assignments menu, and select Settings.
  2. On the Settings page, under Category, select TimeQuest Timing Analyzer.
  3. On the TimeQuest Timing Analyzer subwindow, browse to the .sdc, and click Add.
  4. Click OK.

The following table lists the LVDS timing constraints options and descriptions.

Table 11.  LVDS Timing Constraints Options and Descriptions
Port Name Constraint Type Option Description
GUI Setting SDC command
Input Clock Constraints
rx_inclock create_clock Clock name -name Specifies the name of the LVDS input clock.
Period -period Specifies the clock period (1/fmax).
Rising, Falling -waveform Specifies the clock's rising and falling edges or the duty cycle of the clock. For example, a 10 ns period where the first rising edge occurs at 0 ns and the first falling edge occurs at 5 ns would be written as waveform {0 5}. The difference must be within one period unit, and the rise edge must come before the fall edge. The default edge list is {0 <period>/2}, or a 50 percent duty cycle.
Target [get_ports {<port name>}] Specifies the clock input port name connected to rx_inclock.
Synchronous Input Port Constraints
Minimum, Maximum -max

-min

Specifies the maximum and minimum delay for the data input to the FPGA.
Rise, Fall, Both -clock fall

-clock rises

Specifies the clock's rising and falling edges or the duty cycle of the clock.
rx_in set_input_delay Delay -<delay value> Specifies the data to clock skew in ns.
Target [get_ports {<port name>}] Specifies the data input port name connected to rx_in.
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