Turn on this option to implement the SERDES circuitry in logic cells. The transmitter starts its operation on the first fast clock edge after the PLL is locked. This option is intended for slow speeds. The byte alignment might be different from the dedicated SERDES implementation.

Turn off this option to use the dedicated SERDES circuitry in the device. When you implement the dedicated SERDES in the LVDS transmitter, the SERDES connects to the LVDS transmitter; therefore, the output of the transmitter cannot be assigned to single-ended I/O standards.

This feature is supported in Arria GX, Arria II GX, Arria II GZ, HardCopy® II, HardCopy® III, HardCopy® IV, Stratix, Stratix GX, Stratix II, Stratix II GX, Stratix III, and Stratix IV devices. In Cyclone® series, except Cyclone® V devices, the SERDES is always implemented in logic cells. Cyclone® V devices contain dedicated SERDES circuitry.

If you turn on this option, there is additional delay for the tx_outlock signal to be stable after the tx_locked signal is asserted. Perform gate-level simulation to determine the time for the tx_outclock signal to stabilize.

Number of output channels available for the LVDS transmitter.

If the required number of channels is not available in the list, type the desired number. For example, if the number of channels is 44, the port created is tx_out[43..0]. The legal values depend on the pins available in the device. For the legal values for your device, refer to the relevant device handbook.

Determines the number of parallel bits from the core that the transmitter serializes and sends out. For example, if the deserialization factor is 10 and the number of output channels is 1, the transmitter serializes every 10 parallel bits into a single output channel. If the deserialization factor is 10 and the number of channels is 44, the port created is tx_in[439..0]. For the valid deserialization factors for your device, refer to the relevant device handbook.

When the divide_by_factor port shown in the parameter editor is identical to the deserialization factor, the parameter editor disables the 50/50 duty cycle for x5, x7, and x9 modes.

Turn on this option to use an external PLL to clock the SERDES transmitter. When you turn on this option, the options on the Frequency/PLL settings page are disabled. You must use a separate PLL to provide the clocking source and make the necessary connections. You must ensure your circuit has the correct input and functionality to generate an appropriate clock frequency and is correctly connected to the LVDS transmitter.

When you have a deserialization factor of two, the IP core bypasses SERDES and implements the SERDES functionality in DDR registers. Your design requires a deserialization factor of at least four to turn on the external PLL option.

If you turn off this option, the IP core automatically implements an internal PLL to clock the ALTLVDS_TX block.

For Stratix and Stratix GX devices, if you implement SERDES for your LVDS transmitter using a dedicated SERDES block, you do not have the option to use an external PLL.

Frequency/ PLL Settings (page 4)

The options on this page are available only when you are using internal PLL

Determines the phase alignment of the data transmitted by the core logic array with respect to the tx_inclock clock.

The available values are 0.00, 22.50, 45.00, 67.50, 90.00, 112.50, 135.00, 157.50, 180.00, 202.50, 225.00, 247.50, 270.00, 292.50, 315.00, and 337.50.

The values for this option are device dependent.

Turn on to control the enable port of the fast PLL that the IP core uses with this function.

If the transmitter shares the PLL with other ALTLVDS blocks, and uses the tx_pll_enable port, you must use this port in all the IP core instances and tie the signals together in the design file. If you use a PLL-enabled port in one IP core instance and not another, the PLLs are not shared, and a warning appears during compilation.

Turn on to control the asynchronous reset port of the PLL that the IP core uses with this function.

When the transmitter shares the PLL with other ALTLVDS blocks and uses the pll_areset port, you must use this port in all the IP core instances and tie the signals together in the design file. If you use the pll_areset port in one IP core instance only, the PLLs are not shared and a warning appears during compilation.

The PLL must be reset to set the output clock phase relationships correctly when the PLL loses lock, or if the PLL input reference clock is not stable when the device completes the configuration process.

Turn on this option to add a phase shift of 90° to the clock, which center-aligns the clock in the data. Turn on this option for PLL merging if you also turn on this option for the receiver.

This option is available only for Arria GX, Stratix II, Stratix II GX, and HardCopy® II devices when you implement the SERDES in logic cells, and for Cyclone® II devices.

Turn on this option to reset the PLL automatically whenever the PLL loses lock.

This option is available only for Arria II GX, Arria II GZ, HardCopy® III, HardCopy® IV, Stratix III, and Stratix IV devices when SERDES is implemented in logic cells, and for Cyclone® lll, Cyclone® IV, and Intel® Cyclone® 10 LP devices.

Turn on this option for your LVDS receivers and transmitters to share the same PLL.

Turn on this option if the LVDS receivers and transmitters use the same input clock frequency, deserialization factor, and data rates.

Turn on this option to specify whether input registers are clocked by the tx_inclock signal or tx_coreclock signal. When the PLLs are shared, connect the tx_inclock signal to the same reference clock as the receiver function. For example, if the tx_inclock signal is connected to a 500-MHz input reference clock, and the parallel data rate is not 500 MHz, register the parallel data using the tx_coreclock signal that runs at the output serial data rate divided by the deserialization factor. This frequency matches the parallel data rate from the FPGA core.

If you turn off this option, a warning message appears that directs you to pre-register the inputs in the logic that feeds the transmitter. When you use the Cyclone® series with the ALTLVDS_TX and ALTLVDS_RX IP cores, the interface always sends the most significant bit (MSB) of your parallel data first.

When you use the ALTLVDS_TX IP core, you might get setup timing violations when you use the tx_inclock signal to register the data that feeds the SERDES blocks. The ALTLVDS_TX IP core gives you the choice to register the tx_in[] data with either the tx_inclock or tx_coreclock signal. The default setting is tx_coreclock. Using the tx_coreclock signal to register the data before it feeds the SERDES is the better choice, because it has the optimal phase position to register the data with respect to the high-speed clock that drives the SERDES. Your setup timing violations are eliminated when you use the tx_coreclock signal instead of the tx_inclock signal to register the data in the ALTLVDS_TX IP core. Additionally, you get better timing margins when you use the tx_coreclock signal instead of the tx_inclock signal, even if you do not have timing violations.

Every tx_outclock signal goes through the shift register logic, excluding the following parameter configurations:

• When the outclock_divide_by signal equals to 1, or
• When the outclock_divide_by signal equals to deserialization_factor signal (for odd factors only) and the outclock_duty_cycle signal is 50.

For a SERDES factor of 5 and 9, the outclock divide factors available are 1, 5, and 9. The divide factor of 2 is not available.

For Cyclone® II devices and later, when the implement_in_les parameter is ON, the outclock_duty_cycle of 50 is not supported in the following parameter configurations:

• deserialization_factor signal is 5, 7, or 9
• outclock_divide_by signal equals to deserialization_factor
• outclock_multiply_by is 2

The available values are 0.00, 22.50, 45.00, 67.50, 90.00, 112.50, 135.00, 157.50, 180.00, 202.50, 225.00, 247.50, 270.00, 292.50, 315.00, and 337.50.

The values for this option are device dependent.

This option is available only when you implement the SERDES in logic cells and uses the tx_outclock signal.

The outclock_duty_cycle of 50 is not supported when:

• deserialization_factor signal is 5, 7, or 9
• outclock_divide_by signal equals to deserialization_factor
• outclock_multiply_by is 2

Turn on this option to show the core clock frequency during simulation. Enables the transmitter core clock signal to the registers of all the logic that feeds the LVDS transmitter function. If any other clock feeds the transmit function, your design must implement the clock domain transfer circuitry.

You must add a false path constraint from the slow_clock signal to the fast_clock signal in the ALTLVDS_TX IP core whenever the faster core_clock signal implementation is used for odd deserialization factors.

Specifies the clock resource type fed to the tx_coreclock signal. Allowed values are Auto selection (the Compiler determines the type), Global clock, and Regional clock.

The default value is Auto selection.

Specifies the types of files to be generated. A gray checkmark indicates a file that is automatically generated; a green checkmark indicates an optional file.

Choose from the following types of files:

• AHDL Include file (<function name> .inc)
• VHDL component declaration file (<function name> .cmp)
• Intel® Quartus® Prime symbol file (<function name> .bsf)
• Instantiation template file (<function name> _inst.v or <function name>_inst.vhd
• Verilog HDL block box file (<function name> _bb.v)
• Pin Planner File (<function name> _.ppf)

If you turn on the Generate netlist option, the file for that netlist is also available (<function name> _syn.v).