LVDS SERDES Transmitter / Receiver IP Cores User Guide

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ID 683062
Date 12/15/2017
Public
Document Table of Contents
Document Table of Contents x
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide x
1.1. Features 1.2. Parameter Settings 1.3. Ports 1.4. Prototypes and Component Declarations 1.5. Functional Description 1.6. Simulating Intel® FPGA IP Cores 1.7. Generating ALTLVDS IP Core Using Clear Box Generator 1.8. LVDS SERDES Transmitter/Receiver IP Cores User Guide Archives 1.9. Document Revision History for LVDS SERDES Transmitter/Receiver IP Cores User Guide
1.1. Features x
1.1.1. Resource Utilization and Performance
1.2. Parameter Settings x
1.2.1. ALTLVDS_TX Parameter Settings 1.2.2. ALTLVDS_RX Parameter Settings 1.2.3. Command Line Interface Parameters
1.3. Ports x
1.3.1. ALTLVDS_TX Ports 1.3.2. ALTLVDS_RX Ports
1.4. Prototypes and Component Declarations x
1.4.1. Verilog HDL Prototype 1.4.2. VHDL Component Declaration 1.4.3. VHDL LIBRARY-USE Declaration
1.5. Functional Description x
1.5.1. Receiver Modes 1.5.2. DPA PLL Calibration 1.5.3. Initialization and Reset 1.5.4. Source-Synchronous Timing Analysis and Timing Constraints 1.5.5. Arria II GX, Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V LVDS Package Skew Compensation Report Panel 1.5.6. ALTLVDS IP Core in External PLL Mode
1.5.1. Receiver Modes x
1.5.1.1. DPA Mode 1.5.1.2. Non-DPA Mode 1.5.1.3. Soft-CDR Mode
1.5.1.3. Soft-CDR Mode x
1.5.1.3.1. Clock Forwarding 1.5.1.3.2. Standard Mode 1.5.1.3.3. No Output Register Mode
1.5.2. DPA PLL Calibration x
1.5.2.1. DPA PLL Calibration in Stratix IV ES Devices 1.5.2.2. DPA PLL Calibration in Arria II and Stratix IV Devices and Later 1.5.2.3. Effects of DPA PLL Calibration
1.5.3. Initialization and Reset x
1.5.3.1. Initializing ALTLVDS_TX and ALTLVDS_RX 1.5.3.2. Resetting the DPA 1.5.3.3. Aligning the Word Boundaries 1.5.3.4. Recommended Initialization and Reset Flow
1.5.4. Source-Synchronous Timing Analysis and Timing Constraints x
1.5.4.1. Dedicated SERDES 1.5.4.2. SERDES in LEs 1.5.4.3. Receiver Skew Margin and Transmitter Channel-to-Channel Skew 1.5.4.4. Setting Timing Constraints Using the TimeQuest Timing Analyzer GUI 1.5.4.5. Setting Timing Constraints Manually in the Synopsys Design Constraint File
1.5.4.3. Receiver Skew Margin and Transmitter Channel-to-Channel Skew x
1.5.4.3.1. Obtaining the RSKM Report 1.5.4.3.2. Obtaining the TCCS Report
1.5.4.4. Setting Timing Constraints Using the TimeQuest Timing Analyzer GUI x
1.5.4.4.1. Constraining the Input Clock Signal
1.5.6. ALTLVDS IP Core in External PLL Mode x
1.5.6.1. PLL Clock Signals for LVDS Interface in External PLL Mode 1.5.6.2. External PLL Compensation Mode for ALTLVDS IP Core in External PLL Mode
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide

1.5.4.3. Receiver Skew Margin and Transmitter Channel-to-Channel Skew

Changes in system environment, such as temperature, media (cable, connector, or PCB), and loading, affect the receiver's setup and hold times; internal skew affects the sampling ability of the receiver.

In non-DPA mode, use receiver skew margin (RKSM), receiver channel-to-channel skew (RCCS), and sampling window (SW) specifications to analyze the timing for high-speed source-synchronous differential signals in the receiver data path. The following equation shows the relationship between RSKM, RCCS, and SW.

Figure 4. RSKM


Where:

  • RSKM—is the timing margin between the receiver's clock input and the data input SW.
  • Time unit interval (TUI)—is the time period of the serial data (1/fMAX). Also known as the LVDS period in the TimeQuest Timing Analyzer section in the Intel® Quartus® Prime Compilation Report.
  • SW—is the period of time that the input data must be stable to ensure that data is successfully sampled by the LVDS receiver. The SW is a device property and varies with device speed grade.
  • RCCS— is the timing difference between the fastest and slowest input transitions, including tCO variations and clock skew. Specify RCCS by applying minimum and maximum set_input_delay constraints to the receiver inputs, where RCCS is the difference between the maximum and minimum value.

To obtain accurate RSKM results in the TimeQuest analyzer, specify your RCCS figure using set_input_delay constraints.

The difference between your set_input_delay -min and set_input_delay -max must match your RCCS figure.

For example, to specify an RCCS figure of 0.3 ns: 

set_input_delay -clock rx_inclock -min 0 [get_ports {rx_in*}]
set_input_delay -clock rx_inclock -max 0.3 [get_ports {rx_in*}]

The TimeQuest analyzer takes the 0.3 ns RCCS figure into account during RSKM analysis.

The following figure shows the relationship between the RSKM, RCCS, and SW.

Figure 5. Differential High-Speed Timing Diagram and Timing Budget for Non-DPA Mode


You must calculate the RSKM value to decide whether you can properly sample the data by the LVDS receiver with the given data rate and device. A positive RSKM value indicates the LVDS receiver can properly sample the data; a negative RSKM value indicates the receiver cannot properly sample the data.

The following example shows the RSKM calculation.

Data Rate: 1 Gbps, Board channel-to-channel skew = 200 ps

For Stratix IV devices:

RCCS = 100 ps (pending characterization)

SW = 300 ps (pending characterization)

TUI = 1000 ps

Total RCCS = RCCS + Board channel-to-channel skew= 100 ps + 200 ps

= 300 ps

RSKM= TUI - SW - RCCS

= 1000 ps - 300 ps - 300 ps

= 400 ps > 0

Because the RSKM > 0 ps, receiver non-DPA mode must work correctly.

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