Visible to Intel only — GUID: sam1412665188267
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1.1. Features
1.2. Parameter Settings
1.3. Ports
1.4. Prototypes and Component Declarations
1.5. Functional Description
1.6. Simulating Intel® FPGA IP Cores
1.7. Generating ALTLVDS IP Core Using Clear Box Generator
1.8. LVDS SERDES Transmitter/Receiver IP Cores User Guide Archives
1.9. Document Revision History for LVDS SERDES Transmitter/Receiver IP Cores User Guide
1.5.1. Receiver Modes
1.5.2. DPA PLL Calibration
1.5.3. Initialization and Reset
1.5.4. Source-Synchronous Timing Analysis and Timing Constraints
1.5.5. Arria II GX, Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V LVDS Package Skew Compensation Report Panel
1.5.6. ALTLVDS IP Core in External PLL Mode
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1.5.3.4. Recommended Initialization and Reset Flow
Intel recommends that you follow these steps to initialize and reset the ALTLVDS IP cores:
- During entry into user mode, or anytime in user mode operation when the interface requires a reset, assert the pll_areset and rx_reset ports.
- Deassert the pll_areset port and monitor the rx_locked port (rx_locked is the PLL lock indicator).
- Deassert the rx_reset port after the rx_locked port becomes asserted and stable.
- Apply the DPA training pattern and allow the DPA circuit to lock. (If a training pattern is not available, any data with transitions is required to allow the DPA to lock.) Refer to the respective device data sheet for DPA lock time specifications.
- Wait for the rx_dpa_locked port to assert.
- Beginning with Stratix III, HardCopy III, Arria II GX, and Arria II GZ devices, assert rx_fifo_reset for at least one parallel clock cycle, and then de-assert rx_fifo_reset.
- Assert the rx_cda_reset port for at least one parallel clock cycle, and then deassert the rx_cda_reset port.
- Begin word alignment by applying pulses as required to the rx_channel_data_align port.
- When the word boundaries are established on each channel, the interface is ready for operation.