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1.1. Features
1.2. Parameter Settings
1.3. Ports
1.4. Prototypes and Component Declarations
1.5. Functional Description
1.6. Simulating Intel® FPGA IP Cores
1.7. Generating ALTLVDS IP Core Using Clear Box Generator
1.8. LVDS SERDES Transmitter/Receiver IP Cores User Guide Archives
1.9. Document Revision History for LVDS SERDES Transmitter/Receiver IP Cores User Guide
1.5.1. Receiver Modes
1.5.2. DPA PLL Calibration
1.5.3. Initialization and Reset
1.5.4. Source-Synchronous Timing Analysis and Timing Constraints
1.5.5. Arria II GX, Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V LVDS Package Skew Compensation Report Panel
1.5.6. ALTLVDS IP Core in External PLL Mode
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1.5.6.2. External PLL Compensation Mode for ALTLVDS IP Core in External PLL Mode
If you instantiate the ALTLVDS IP core in external PLL mode, Intel recommends that you set up the data rate and clocking with the PLL IP core.
Note: For Stratix® IV, Arria® II, Cyclone® IV, and Intel® Cyclone® 10 LP devices, use the ALTPLL IP core. For Stratix® V, Arria® V, and Cyclone® V devices use the Altera PLL IP core.
- For Arria® V, Arria® V GZ, and Stratix® V devices with ALTLVDS_RX configured in non-DPA mode, the external PLL must be in LVDS compensation mode.
- For Cyclone® V devices, LVDS interfaces placed on the all edges must be in LVDS compensation mode.
For more information about PLL compensation modes, refer to the PLL chapter of the relevant device handbook.