LVDS SERDES Transmitter / Receiver IP Cores User Guide

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ID 683062
Date 12/15/2017
Public
Document Table of Contents
Document Table of Contents x
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide x
1.1. Features 1.2. Parameter Settings 1.3. Ports 1.4. Prototypes and Component Declarations 1.5. Functional Description 1.6. Simulating Intel® FPGA IP Cores 1.7. Generating ALTLVDS IP Core Using Clear Box Generator 1.8. LVDS SERDES Transmitter/Receiver IP Cores User Guide Archives 1.9. Document Revision History for LVDS SERDES Transmitter/Receiver IP Cores User Guide
1.1. Features x
1.1.1. Resource Utilization and Performance
1.2. Parameter Settings x
1.2.1. ALTLVDS_TX Parameter Settings 1.2.2. ALTLVDS_RX Parameter Settings 1.2.3. Command Line Interface Parameters
1.3. Ports x
1.3.1. ALTLVDS_TX Ports 1.3.2. ALTLVDS_RX Ports
1.4. Prototypes and Component Declarations x
1.4.1. Verilog HDL Prototype 1.4.2. VHDL Component Declaration 1.4.3. VHDL LIBRARY-USE Declaration
1.5. Functional Description x
1.5.1. Receiver Modes 1.5.2. DPA PLL Calibration 1.5.3. Initialization and Reset 1.5.4. Source-Synchronous Timing Analysis and Timing Constraints 1.5.5. Arria II GX, Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V LVDS Package Skew Compensation Report Panel 1.5.6. ALTLVDS IP Core in External PLL Mode
1.5.1. Receiver Modes x
1.5.1.1. DPA Mode 1.5.1.2. Non-DPA Mode 1.5.1.3. Soft-CDR Mode
1.5.1.3. Soft-CDR Mode x
1.5.1.3.1. Clock Forwarding 1.5.1.3.2. Standard Mode 1.5.1.3.3. No Output Register Mode
1.5.2. DPA PLL Calibration x
1.5.2.1. DPA PLL Calibration in Stratix IV ES Devices 1.5.2.2. DPA PLL Calibration in Arria II and Stratix IV Devices and Later 1.5.2.3. Effects of DPA PLL Calibration
1.5.3. Initialization and Reset x
1.5.3.1. Initializing ALTLVDS_TX and ALTLVDS_RX 1.5.3.2. Resetting the DPA 1.5.3.3. Aligning the Word Boundaries 1.5.3.4. Recommended Initialization and Reset Flow
1.5.4. Source-Synchronous Timing Analysis and Timing Constraints x
1.5.4.1. Dedicated SERDES 1.5.4.2. SERDES in LEs 1.5.4.3. Receiver Skew Margin and Transmitter Channel-to-Channel Skew 1.5.4.4. Setting Timing Constraints Using the TimeQuest Timing Analyzer GUI 1.5.4.5. Setting Timing Constraints Manually in the Synopsys Design Constraint File
1.5.4.3. Receiver Skew Margin and Transmitter Channel-to-Channel Skew x
1.5.4.3.1. Obtaining the RSKM Report 1.5.4.3.2. Obtaining the TCCS Report
1.5.4.4. Setting Timing Constraints Using the TimeQuest Timing Analyzer GUI x
1.5.4.4.1. Constraining the Input Clock Signal
1.5.6. ALTLVDS IP Core in External PLL Mode x
1.5.6.1. PLL Clock Signals for LVDS Interface in External PLL Mode 1.5.6.2. External PLL Compensation Mode for ALTLVDS IP Core in External PLL Mode
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide

1.5.3.1. Initializing ALTLVDS_TX and ALTLVDS_RX

With the ALTLVDS_TX and ALTLVDS_RX IP cores, the PLL is locked to the reference clock prior to implementing the SERDES blocks for data transfer. The PLL starts to lock to the reference clock during device initialization. The PLL is operational when the PLL achieves lock during user mode. If the clock reference is not stable during device initialization, the PLL output clock phase shifts becomes corrupted.

When the PLL output clock phase shifts are not set correctly, the data transfer between the high-speed LVDS domain and the low-speed parallel domain might not be successful, which leads to data corruption. Assert the pll_areset port for at least 10 ns, and then deassert the pll_areset port and wait until the PLL lock becomes stable. After the PLL lock port asserts and is stable, the SERDES blocks are ready for operation.

When using DPA, further steps are required for initialization and reset recovery. The DPA circuit samples the incoming data and finds the optimal phase tap from the PLL to capture the data on a receiver channel-by-channel basis. If the PLL has not locked to a stable clock source, the DPA circuit might lock pre-maturely to a non-ideal phase tap. Use the rx_reset port to keep the DPA in reset until the PLL lock signal is asserted and stable.

In Stratix GX, Stratix II, Stratix II GX, HardCopy II, and Arria GX devices, when using the rx_reset port, the ALTLVDS_RX parameter editor allows you to choose whether or not to automatically reset the bit serial FIFO when the rx_dpa_locked signal asserts for the first time. This is a useful feature because it keeps the synchronizer FIFO in reset until the DPA locks. To provide optimal timing between the DPA domain, it is important to keep the FIFO in reset until the DPA locks.

With Stratix III, HardCopy III, Arria II GX, Arria II GZ devices and later generations of these devices, the rx_dpa_lock signal asserts only after a specific number of transitions are detected in the parallel data stream. You must not assert rx_fifo_reset port until the rx_dpa_lock signal asserts, otherwise, there will be no data transitions in the parallel data, and the rx_dpa_lock signal will never assert.

Note: Intel recommends asserting the rx_fifo_reset port after the rx_dpa_locked signal asserts, and then deassert the rx_fifo_reset port to begin receiving data.

Each time the DPA shifts the phase taps during normal operation to track variations between the relationship of the reference clock source and the data, the timing margin for the data transfer between clock domains is reduced.

For Stratix GX, Stratix II, Stratix II GX, HardCopy II, and Arria GX devices, when the ALTLVDS_RX IP core deasserts the rx_dpa_locked port to indicate that the DPA has selected a new phase tap to capture the data. You can choose the options in the ALTLVDS_RX parameter editor if you want the DPA lock signal to deassert after one phase step, or after two phase steps in the same direction (check device family availability for this option).

With Stratix III, HardCopy III, Arria II GX, Arria II GZ devices and later generations of these devices, the ALTLVDS_RX asserts the rx_dpa_locked port upon initial DPA lock. This port remains asserted throughout the operation until the ALTLVDS_RX IP core asserts the rx_reset or rx_dpa_lock_reset ports. The rx_dpa_locked port does not indicate if the DPA has selected a new phase.

Note: Intel recommends using the data checkers to ensure data accuracy.
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